Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes
Nano-CMOS Design for Manufacturability examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. In addition to discussing the difficulties brought on by the continued dimensional scaling in conformance with Moore's law, the authors also tackle complex issues in the design process to overcome the difficulties, including the use of a functional first silicon to support a predictable product ramp. Moreover, they introduce several emerging concepts, including stress proximity effects, contour-based extraction, and design process interactions.
This book is the sequel to Nano-CMOS Circuit and Physical Design, taking design to technology nodes beyond 65nm geometries. It is divided into three parts:
Part One, Newly Exacerbated Effects, introduces the newly exacerbated effects that require designers' attention, beginning with a discussion of the lithography aspects of DFM, followed by the impact of layout on transistor performance
Part Two, Design Solutions, examines how to mitigate the impact of process effects, discussing the methodology needed to make sub-wavelength patterning technology work in manufacturing, as well as design solutions to deal with signal, power integrity, WELL, stress proximity effects, and process variability
Part Three, The Road to DFM, describes new tools needed to support DFM efforts, including an auto-correction tool capable of fixing the layout of cells with multiple optimization goals, followed by a look ahead into the future of DFM
Throughout the book, real-world examples simplify complex concepts, helping readers see how they can successfully handle projects on Nano-CMOS nodes. It provides a bridge that allows engineers to go from physical and circuit design to fabrication processing and, in short, make designs that are not only functional, but that also meet power and performance goals within the design schedule.
1.1 DFM - Value proposition.
1.2 Deficiencies in Boolean-based Design Rules in the sub-wavelength regime .
1.3 Impact of Variability on Yield and Performance.
1.4 The industry challenge - disappearing process window.
1.5 Mobility enhancement techniques - a new source of variability induced by design process interaction.
1.6 Design dependency of chip surface topology.
1.7 Newly exacerbated narrow width effect in nano-CMOS nodes.
1.8 Well proximity effect.
1.9 Scaling beyond 65nm drives the need for model based DFM solutions.
PART 1: NEWLY EXACERBATED EFFECTS.
2. Lithography related Aspects of DFM.
2.1 Economic motivations for DFM.
2.2 Lithographic tools and techniques for advanced technology nodes.
2.3 Lithography limited yield.
2.4 Lithography driven DFM Solutions.
3. Interaction of layout with transistor performance and stress engineering techniques.
3.2 Impact of stress on transistor performance.
3.3 Stress propagation.
3.4 Stress sources.
3.5 Introducing stress into transistors.
PART 2: DESIGN SOLUTIONS.
4. Signal and Power Integrity.
4.2 Interconnect Resistance, Capacitance and Inductance.
4.3 Inductance Effects on Interconnect.
5. Analog and Mixed Signal Circuit Design for Yield and Manufacturability.
5.3 Device Selection.
5.4 Device Size Heart Beat.
5.5 Device Matching.
5.6 Design Guidelines.
5.7 Layout Guidelines.
6. Design for Variability, Performance and Yield.
6.2 Impact of variations (introduced by both process and circuit operation) on the design.
6.3 Some Parametric Fluctuations with new implications for design .
6.4 Process Variations in Interconnects.
6.5 Impact of Deep Sub-Micron Integration in SRAMs.
6.6 Impact of Layout Styles on Manufacturability, Yield and Scalability.
6.7 Design for variations.
PART 3: THE ROAD TO DFM.
7. Nano-CMOS design tools: Beyond model-based analysis and correction.
7.2 Electrical Design for Manufacturability (DFM).
7.3 Criticality Aware DFM.
7.4 On Guardbands, Statistics, and Gaps.
7.5 Opportunistic Mindsets.
7.6 Futures at ó 45nm .
Franz Zach, PhD, is Senior Director at PDF Solutions, where he is involved in integrated yield ramps at advanced technology nodes.
Victor Moroz, PhD, is a Principal Engineer at Synopsys. He focuses on semiconductor physics, including silicon process integration, teaching undergraduate and graduate students, and developing process simulation and DFM tools.
Anurag Mittal, PhD, Yale University, has co-developed the world's first truly CMOS-compatible Flash technology. He has several papers, invited talks, and patents to his credit. Currently he is Director of Technology & Applications at Takumi Inc., where he is developing novel EDA solutions on Design for Variability & Reliability.
Greg W. Starr, PhD, is a Supervising Principal Engineer at Xilinx, where he is responsible for advanced serial IO development on advanced processes.
Andrew Kahng, PhD, is Professor of CSE and ECE at the University of California, San Diego, and the CTO of Blaze DFM. His research focuses on integrated circuit physical design and design for manufacturability. Dr. Kahng has published more than 300 journal and conference papers.
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Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes (US $130.00)
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