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Advanced Circuits for Emerging Technologies

ISBN: 978-0-470-90005-5
632 pages
May 2012
Advanced Circuits for Emerging Technologies (0470900059) cover image
The book will address the-state-of-the-art in integrated circuit design in the context of emerging systems. New exciting opportunities in body area networks, wireless communications, data networking, and optical imaging are discussed. Emerging materials that can take system performance beyond standard CMOS, like Silicon on Insulator (SOI), Silicon Germanium (SiGe), and Indium Phosphide (InP) are explored. Three-dimensional (3-D) CMOS integration and co-integration with sensor technology are described as well. The book is a must for anyone serious about circuit design for future technologies.

The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with integrated circuit background. The book will be also used as a recommended reading and supplementary material in graduate course curriculum. Intended audience is professionals working in the integrated circuit design field. Their job titles might be : design engineer, product manager, marketing manager, design team leader, etc. The book will be also used by graduate students. Many of the chapter authors are University Professors.

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Preface xiii

Contributors xv

PART I DIGITAL DESIGN AND POWER MANAGEMENT

1 DESIGN IN THE ENERGY–DELAY SPACE 3
Massimo Alioto, Elio Consoli, and Gaetano Palumbo

1.1 Introduction 3

1.2 Energy and Delay Modeling 4

1.3 Energy–Delay Space Analysis and Hardware-Intensity 14

1.4 Energy-Efficient Design of Digital Circuits 20

1.5 Design of Energy-Efficient Pipelined Systems 29

1.6 Conclusion 36

References 37

2 SUBTHRESHOLD SOURCE-COUPLED LOGIC 41
Armin Tajalli and Yusuf Leblebici

2.1 Introduction 41

2.2 Ultralow Power CMOS Logic: Design and Tradeoffs 43

2.3 Subthreshold Source-Coupled Logic 47

2.4 Power-Frequency Scaling 51

2.5 Conclusions 53

References 55

3 ULTRALOW-VOLTAGE DESIGN OF NANOMETER CMOS CIRCUITS FOR SMART ENERGY-AUTONOMOUS SYSTEMS 57
David Bol

3.1 Introduction 57

3.2 Impact of Technology Scaling on Subthreshold MOSFET Characteristics 61

3.3 Scaling Trend of the Minimum-Energy Point 63

3.4 Practical Energy of Nanometer ULV Circuits under Robustness and Timing Constraints 69

3.5 Technology/Circuit Methodology and Roadmap for ULV Design in the Nanometer Era 75

3.6 Conclusion 78

References 79

4 IMPAIRMENT-AWARE ANALOG CIRCUIT DESIGN BY RECONFIGURING FEEDBACK SYSTEMS 85
Ping-Ying Wang

4.1 Introduction 86

4.2 Theorem of Impairment-Aware Analog Design in Feedback Systems 86

4.3 Practical Implementations 89

4.4 Measured Results 96

4.5 Conclusions 99

References 100

5 ROM-BASED LOGIC DESIGN: A LOW-POWER DESIGN PERSPECTIVE 103
Bipul C. Paul

5.1 Introduction 103

5.2 RBL Design 105

5.3 RBL Adder 108

5.4 RBL Multiplier 111

5.5 Conclusions 116

References 117

6 POWER MANAGEMENT: ENABLING TECHNOLOGY 119
Lou Hutter and Felicia James

6.1 Macroeconomic Drivers for Power Technologies 119

6.2 Market Trends 122

6.3 Application Examples 123

6.4 Technology Implications and Trends 124

6.5 Current Technologies and Capabilities 130

6.6 Specific Application Example 140

6.7 Emerging Technologies 142

6.8 Conclusion 143

References 143

7 ULTRALOW POWER MANAGEMENT CIRCUIT FOR OPTIMAL ENERGY HARVESTING IN WIRELESS BODY AREA NETWORK 147
Yen Kheng Tan, Yuanjin Zheng, and Huey Chian Foong

7.1 Introduction 147

7.2 Wireless Body Area Network 148

7.3 Optimal Energy Harvesting System 159

7.4 Ultralow Power Management Integrated Circuit for Solar Energy Harvesting System 163

7.5 Conclusions 171

References 171

PART II ANALOG AND RF DESIGN

8 ANALOG CIRCUIT DESIGN FOR SOI 177
Andrew Marshall

8.1 SOI Devices 177

8.2 Partially Depleted SOI 178

8.3 FDSOI and FinFET 181

8.4 Device Considerations (FDSOI AND PDSOI) 181

8.5 Analog Circuit Building Blocks 184

8.6 Operational Amplifiers 189

8.7 Operational Transconductance Amplifier 193

8.8 Radio Frequency Low-Noise Amplifier 197

8.9 Mixers and Analog Multipliers 197

8.10 Analog to Digital and Digital to Analog Converters 201

8.11 Summary 204

References 204

9 FREQUENCY GENERATION AND CONTROL WITH SELF-REFERENCED CMOS OSCILLATORS 207
Michael S. McCorquodale, Nathaniel Gaskin, and Vidyabhusan Gupta

9.1 Introduction 207

9.2 Self-Referenced CMOS Oscillators 211

9.3 Packaging 225

9.4 Conclusion 234

References 235

10 SYNTHESIS OF STATIC AND DYNAMIC TRANSLINEAR CIRCUITS 239
Bradley A. Minch

10.1 Translinear Circuits: What Is In a Name? 239

10.2 The Scope of Translinear Circuits 242

10.3 Static and Dynamic Translinear Circuit Synthesis 242

10.4 Static Translinear Circuit Synthesis Examples 250

10.5 Dynamic Translinear Circuit Synthesis Examples 260

References 272

11 MICROWATT POWER CMOS ANALOG CIRCUIT DESIGNS: ULTRALOW POWER LSIs FOR POWER-AWARE APPLICATIONS 277
Ken Ueno and Tetsuya Hirose

11.1 Introduction 277

11.2 Subthreshold Characteristics in a MOSFET 279

11.3 Low-Power Voltage Reference Circuits 284

11.4 Low-Power Current Reference Circuits 293

11.5 Example of Power-Aware LSI Applications: CMOS Smart Sensor for Monitoring the Quality of Perishables 299

11.6 Conclusion and Discussion 308

References 310

12 HIGH-SPEED CURRENT-MODE DATA DRIVERS FOR AMOLED DISPLAYS 313
Yong-Joon Jeon and Gyu-Hyeong Cho

12.1 Introduction 313

12.2 Current-Mode Drivers in Representation of the Second-Generation Current Conveyor 316

12.3 Improved Transient Current Feed-Forward Output Buffer 317

12.4 Push-Pull Transient Current Feedforward Output Buffer 324

12.5 Conclusion 332

References 333

13 RF TRANSCEIVERS FOR WIRELESS APPLICATIONS 335
Alireza Zolfaghari, Hooman Darabi, and Henrik Jensen

13.1 Transmitter Architectures 335

13.2 Cartesian Transmitters 336

13.3 Constant-Envelope Transmitters Using Phase Modulated Loops 339

13.4 Polar Transmitters 340

13.5 Case Studies 346

References 350

PART III DEVICE LAYOUT AND RELIABILITY

14 TECHNOLOGY-AWARE COMMUNICATION ARCHITECTURE DESIGN FOR PARALLEL HARDWARE PLATFORMS 355
Davide Bertozzi, Alessandro Strano, Daniele Ludovici, and Francisco Gilabert

14.1 Introduction 355

14.2 NoC Building Blocks: The Switch 358

14.3 NoC Connectivity Pattern 362

14.4 NoCs and the GALS Paradigm 372

14.5 Putting Everything Together: Technology-Aware Network Connectivity 385

14.6 Looking Forward: Mesochronous Synchronization 389

14.7 Conclusions 390

References 390

15 DESIGN AND OPTIMIZATION OF INTEGRATED TRANSMISSION LINES ON SCALED CMOS TECHNOLOGIES 393
Federico Vecchi, Matteo Repossi, Wissam Eyssa, Paolo Arcioni, and Francesco Svelto

15.1 Introduction 393

15.2 Coplanar Waveguides 394

15.3 Shielded Transmission Lines 397

15.4 Accurate and Fast Analysis of Periodic Lines 402

15.5 Design and Experimental Results 406

15.6 Conclusions 411

References 413

16 ON-CHIP SURFING INTERCONNECT 415
Suwen Yang and Mark Greenstreet

16.1 Introduction 415

16.2 Surfing 417

16.3 Surfing DLLs 419

16.4 Pipelined Clock Forwarding 423

16.5 Source Synchronous Surfing 427

16.6 Surfing Handshakes 431

16.7 Summary 435

References 436

17 ON-CHIP SPIRAL INDUCTORS WITH INTEGRATED MAGNETIC MATERIALS 439
Wei Xu, Saurabh Sinha, Hao Wu, Tawab Dastagir, Yu Cao, and Hongbin Yu

17.1 Introduction 439

17.2 Previous Work 441

17.3 Magnetic Materials 443

17.4 Simulation Study 447

17.5 Device Fabrication 451

17.6 Measurement Results 453

17.7 Potential Applications of On-Chip Spiral Inductors with Magnetic Materials 455

17.8 Conclusion 458

References 458

18 RELIABILITY OF NANOELECTRONIC VLSI 463
Milos Stanisavljevic, Alexandre Schmid, and Yusuf Leblebici

18.1 Introduction 463

18.2 Increased Defect Density and Reliability 464

18.3 Reliability Evaluation 466

18.4 Historically Important CAD Tools 467

18.5 Recent Progress 469

18.6 Monte Carlo Reliability Evaluation Tool 473

18.7 Fault-Tolerant Computing 476

18.8 Conclusions 476

References 477

19 TEMPERATURE MONITORING ISSUES IN NANOMETER CMOS INTEGRATED CIRCUITS 483
Pablo Ituero and Marisa López-Vallejo

19.1 Introduction 483

19.2 From Where Does Heat Come in Nanometer Circuits? 485

19.3 Harmful Effects Due to Temperature in VLSI Chips 488

19.4 Temperature Sensing for DTM 493

19.5 Thermal Modeling 498

19.6 Thermal Sensor Placement and Allocation 500

19.7 Temperature Monitoring Networks 503

19.8 Conclusions 505

References 505

PART IV CIRCUIT TESTING

20 LOW-POWER TESTING FOR LOW-POWER LSI CIRCUITS 511
Xiaoqing Wen and Yervant Zorian

20.1 Introduction 511

20.2 Test Power Problem in Logic LSI Testing 513

20.3 Basic Strategies to Test Power Reduction 515

20.4 Shift Power Reduction 517

20.5 Capture Power Reduction 519

20.6 Toward Next-Generation Low-Power Testing Solutions 522

20.7 Summary 525

References 526

21 CHECKERS FOR ONLINE SELF-TESTING OF ANALOG CIRCUITS 529
Haralampos-G. Stratigopoulos and Yiorgos Makris

21.1 Introduction 529

21.2 Time-Invariant Linear Circuits 531

21.3 Fully Differential Circuits 542

21.4 Conclusions 553

References 553

22 DESIGN AND TEST OF ROBUST CMOS RF AND MM-WAVE RADIOS 557
Sleiman Bou-Sleiman and Mohammed Ismail

22.1 Introduction 557

22.2 Why Robust RF and mm-Wave ICs? 558

22.3 Design Methodology for First-Time-Right Radio SoCs 564

22.4 Robust RF and mm-Wave Radio Transceivers 571

22.5 Summary 578

References 579

23 CONTACTLESS TESTING AND DIAGNOSIS TECHNIQUES 581
Selahattin Sayil

23.1 Introduction 581

23.2 Electron-Beam Method 582

23.3 Photoemissive Probing 583

23.4 Electro-Optic Probing 584

23.5 Charge Density Probing 587

23.6 Photoexcitation Probe Techniques 588

23.7 Electric Force Microscopy 589

23.8 Capacitive Coupling Method 590

23.9 Dynamic Internal Testing of CMOS using Hot-Carrier Luminescence 591

23.10All-Silicon Optical Contactless Testing of Integrated Circuits 592

23.11Conclusion 596

References 596

INDEX 599

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Krzysztof (Kris) Iniewski, PhD, manages R&D developments at Redlen Technologies. He is also an executive director at CMOS Emerging Technologies. A former associate professor in the Electrical Engineering and Computer Engineering and Computer Engineering Department at the University of Alberta, Dr. Iniewski’s Main research interest is in IC design for medical and networking applications.

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