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Advanced Frequency Synthesis by Phase Lock

ISBN: 978-0-470-91566-0
312 pages
August 2011, Wiley-IEEE Press
Advanced Frequency Synthesis by Phase Lock (0470915668) cover image

Description

The latest frequency synthesis techniques, including sigma-delta, Diophantine, and all-digital

Sigma-delta is a frequency synthesis technique that has risen in popularity over the past decade due to its intensely digital nature and its ability to promote miniaturization. A continuation of the popular Frequency Synthesis by Phase Lock, Second Edition, this timely resource provides a broad introduction to sigma-delta by pairing practical simulation results with cutting-edge research. Advanced Frequency Synthesis by Phase Lock discusses both sigma-delta and fractional-n—the still-in-use forerunner to sigma-delta—employing Simulink® models and detailed simulations of results to promote a deeper understanding.

After a brief introduction, the book shows how spurs are produced at the synthesizer output by the basic process and different methods for overcoming them. It investigates how various defects in sigma-delta synthesis contribute to spurs or noise in the synthesized signal. Synthesizer configurations are analyzed, and it is revealed how to trade off the various noise sources by choosing loop parameters. Other sigma-delta synthesis architectures are then reviewed.

The Simulink simulation models that provided data for the preceding discussions are described, providing guidance in making use of such models for further exploration. Next, another method for achieving wide loop bandwidth simultaneously with fine resolution—the Diophantine Frequency Synthesizer—is introduced. Operation at extreme bandwidths is also covered, further describing the analysis of synthesizers that push their bandwidths close to the sampling-frequency limit. Lastly, the book reviews a newly important technology that is poised to become widely used in high-production consumer electronics—all-digital frequency synthesis.

Detailed appendices provide in-depth discussion on various stages of development, and many related resources are available for download, including Simulink models, MATLAB® scripts, spreadsheets, and executable programs. All these features make this authoritative reference ideal for electrical engineers who want to achieve an understanding of sigma-delta frequency synthesis and an awareness of the latest developments in the field.

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Table of Contents

PREFACE xv

SYMBOLS LIST AND GLOSSARY xix

1 INTRODUCTION 1

1.1 Phase-Locked Synthesizer 2

1.2 Fractional-N Frequency Synthesis 3

1.3 Representing a Change in Divide Number 3

1.4 Units 5

1.5 Representing Phase Noise 5

1.6 Phase Noise at the Synthesizer Output 7

1.7 Observing the Output Spectrum 7

2 FRACTIONAL-N AND BASIC SD SYNTHESIZERS 9

2.1 First-Order Fractional-N 9

2.1.1 Canceling Quantization Noise 11

2.1.2 Cancellation with a PFD 13

2.1.3 Cancellation Techniques 15

2.1.4 Spectrum without Cancellation 16

2.1.5 Influence of N 17

2.2 Second-Order Fractional-N 17

2.2.1 Purpose 17

2.2.2 Form 18

2.2.3 Performance 19

2.2.4 Interpreting the Spectrum 21

2.3 Higher Order Fractional-N 24

2.3.1 Constant Sampling Rate 25

2.3.2 Noise Shaping Versus Cancellation 28

2.3.3 Effect of a Varying Sampling Rate 28

2.4 Spectrums with Constant Sampling Rate 31

2.4.1 100.625 MHz with Zero Initial Condition 31

2.4.2 100.62515... with Zero Initial Condition 34

2.4.3 100.625 MHz with Seed 36

2.5 Summary of Spectrums 36

2.6 Summary 36

3 OTHER SPURIOUS REDUCTION TECHNIQUES 39

3.1 LSB Dither 39

3.2 Maximum Sequence Length 43

3.3 Shortened Accumulators and Lower Primes 48

3.4 Long Sequence 51

3.5 Summary 53

4 DEFECTS IN SD SYNTHESIZERS 55

4.1 Noise Models 55

4.1.1 VCO Noise 55

4.1.2 Basic-Reference Noise 56

4.1.3 Equivalent Input Noise 56

4.1.4 SD Quantization Noise 57

4.1.5 Parameter Dependence 57

4.1.6 Synthesizer Output Noise 57

4.1.6.1 Nominal Parameters 59

4.1.6.2 Higher Fout 60

4.1.6.3 Higher Fref 62

4.1.6.4 Summary 63

4.2 Levels of Other Noise in SD Synthesizers 64

4.2.1 Dither 65

4.2.2 Varying Sample Rate 65

4.2.3 Mismatched (Unbalanced) Charge Pumps 66

4.2.4 Levels for All Four Loop Configurations 67

4.2.5 Simple Charge Pump 69

4.2.6 System Performance 71

4.3 Noise Sources, Equivalent Input Noise 71

4.3.1 Without SD Modulation 72

4.3.2 Increase with SD Modulation 73

4.4 Discrete Sidebands 74

4.4.1 At Offsets Related to ffract 74

4.4.1.1 Due to Current Mismatch 74

4.4.1.2 Not Necessarily Related to Mismatch 75

4.4.2 At Offsets of nFref 75

4.4.2.1 Due to SD Modulation 76

4.4.2.2 Due to Delays in the PFD 77

4.4.2.3 Due to Leakage Current 77

4.4.2.4 Due to All Three 77

4.4.2.5 With Resampling 78

4.4.2.6 Significance of Levels 78

4.4.3 Charge Pump Dead Zone 80

4.5 Summary 80

5 OTHER SD ARCHITECTURES 81

5.1 Stability 81

5.2 Feedback 82

5.3 Feedforward 85

5.4 Quantizer Offset 89

5.5 MASH-n1n2n3 91

5.6 Cancellation of Quantization Noise in the General Modulator 92

5.7 Fractional Swallows 93

5.7.1 Resulting Spurs 96

5.7.2 Estimate of Achievable Suppression 96

5.7.3 Fractional Swallows in a SD Synthesizer 96

5.8 Hardware Reduction 97

5.8.1 Analysis 97

5.8.2 Simulation 100

6 SIMULATION 103

6.1 SandH.mdl 103

6.1.1 The Synthesizer Loop 105

6.1.2 MASH Modulator 105

6.1.3 Setting Parameters 105

6.1.4 Accumulator Size 106

6.1.5 Scopes 107

6.1.6 Spectrum Analyzers 107

6.1.7 Spectrums Observed 108

6.1.8 Reason for Frequency Conversion 110

6.1.9 Synchronization 111

6.2 SandHreverse.mdl 111

6.3 CPandI.mdl 111

6.4 Dither.mdl 111

6.5 HandK.mdl 113

6.6 SimplePD.mdl 114

6.7 CPandIplus.mdl 114

6.7.1 CP Balance 114

6.7.2 PFD Delays 116

6.7.3 Data Acquisition 116

6.7.4 Log Plots 116

6.8 CPandITrunc.mdl 117

6.9 Adapting a Model 118

6.10 EFeedback.mdl 118

6.11 FeedForward.mdl 120

6.12 MASH modulator scripts 120

6.13 SynStep__.mdl 121

6.14 Other Methods 121

7 DIOPHANTINE SYNTHESIZER 123

7.1 Two-Loop Synthesizer 124

7.2 Multi Loop Synthesizers 126

7.3 MATLAB Scripts 126

7.3.1 loop2tune 126

7.3.2 loopxtune 128

7.3.3 Algorithm 128

7.4 Signal Mixing 129

7.5 Reference-Frequency Coupling 132

7.6 Center Frequencies 133

8 OPERATION AT EXTREME BANDWIDTHS 135

8.1 Determining the Effects of Sampling 135

8.2 A Particular Case 136

8.3 When are Sampling Effects Important?  141

8.4 Computer Program 141

8.5 Sampling Effects in SD Synthesizers 141

9 ALL-DIGITAL FREQUENCY SYNTHESIZERS 145

9.1 The Flying Adder Synthesizer 146

9.1.1 The Concept 146

9.1.2 Frequencies Generated 147

9.1.3 Jitter 149

9.1.4 Suppression of Spurs 150

9.1.5 Further Development 151

9.2 ADPLL Synthesizer 151

9.2.1 ADPLL Concept 151

9.2.2 The Numbers 152

9.2.3 Mathematical Representation 152

9.2.4 DCO 153

9.2.5 Loop Filter 154

9.2.6 Synchronization 154

9.2.7 Phase Noise 154

9.2.7.1 In-Band Noise, Critical Source 154

9.2.7.2 Improving Resolution 155

9.2.8 Reference Spurs 157

9.2.9 Fractional Spurs 157

9.2.10 Modulation Response 159

9.2.11 SD Cancellation 159

9.2.12 Simulation 159

9.2.13 Dead Zone 160

APPENDIX A. ALL DIGITAL 163

APPENDIX C. FRACTIONAL CANCELLATION 171

APPENDIX E. EXCESS PPSD 177

APPENDIX F. REFERENCES TO FS2 183

APPENDIX G. USING GSMPL 185

APPENDIX H. SAMPLE-AND-HOLD CIRCUIT 195

APPENDIX L. LOOP RESPONSE 207

APPENDIX M. MASH PSD 215

APPENDIX N. SAMPLED NOISE 225

APPENDIX O. OSCILLATOR SPECTRUMS 229

APPENDIX P. PHASE DETECTORS 231

APPENDIX Q. QUANTIZATION PPSD 233

APPENDIX R. REFERENCE FREQUENCY SPURS 241

APPENDIX S. SPECTRUM ANALYSIS 249

APPENDIX T. TOOLBOXES 259

APPENDIX U. NOISE PRODUCED BY CHARGE PUMP

CURRENT UNBALANCE (MISMATCH) 261

APPENDIX W. GETTING FILES FROM THE WILEY

INTERNET SITE 265

APPENDIX X. SOME TABLES 267

END NOTES 269

REFERENCES 277

INDEX 283

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Author Information

William F. Egan, PhD, is a lecturer in electrical engineering at Santa Clara University, California. Formerly, he was a principal engineer at TRW ESL and a senior technologist at GTE Government Systems.

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advanced_frequency_synthesis_by_phaselock.zip 35.27 KB Click to Download
models.zip 397.30 KB Click to Download
scripts.zip 26.81 KB Click to Download
spreadsheets.zip 220.86 KB Click to Download
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