 Design Through Verilog HDL
ISBN: 978-0-471-44148-9
Hardcover
472 pages
November 2003, Wiley-IEEE Press
US $132.00
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ACKNOWLEDGEMENTS.
1 INTRODUCTION TO VLSI DESIGN.
1.1 INTRODUCTION.
1.2 CONVENTIONAL APPROACH TO DIGITAL DESIGN.
1.3 VLSI DESIGN.
1.4 ASIC DESIGN FLOW.
1.5 ROLE OF HDL.
2 INTRODUCTION TO VERILOG.
2.1 VERILOG AS AN HDL.
2.2 LEVELS OF DESIGN DESCRIPTION.
2.3 CONCURRENCY.
2.4 SIMULATION AND SYNTHESIS.
2.5 FUNCTIONAL VERIFICATION.
2.6 SYSTEM TASKS.
2.7 PROGRAMMING LANGUAGE INTERFACE (PLI).
2.8 MODULE.
2.9 SIMULATION AND SYNTHESIS TOOLS.
2.10 TEST BENCHES.
3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG.
3.1 INTRODUCTION.
3.2 KEYWORDS.
3.3 IDENTIFIERS.
3.4 WHITE SPACE CHARACTERS.
3.5 COMMENTS.
3.6 NUMBERS.
3.7 STRINGS.
3.8 LOGIC VALUES.
3.9 STRENGTHS.
3.10 DATA TYPES.
3.11 SCALARS AND VECTORS.
3.12 PARAMETERS.
3.13 MEMORY.
3.14 OPERATORS.
3.15 SYSTEM TASKS.
3.16 EXERCISES.
4 GATE LEVEL MODELING – 1.
4.1 INTRODUCTION.
4.2 AND GATE PRIMITIVE.
4.3 MODULE STRUCTURE.
4.4 OTHER GATE PRIMITIVES.
4.5 ILLUSTRATIVE EXAMPLES.
4.6 TRI-STATE GATES.
4.7 ARRAY OF INSTANCES OF PRIMITIVES.
4.8 ADDITIONAL EXAMPLES.
4.9 EXERCISES.
5 GATE LEVEL MODELING – 2.
5.1 INTRODUCTION.
5.2 DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES.
5.3 DELAYS.
5.4 STRENGTHS AND CONTENTION RESOLUTION.
5.5 NET TYPES.
5.6 DESIGN OF BASIC CIRCUITS.
5.7 EXERCISES.
6 MODELING AT DATA FLOW LEVEL.
6.1 INTRODUCTION.
6.2 CONTINUOUS ASSIGNMENT STRUCTURES.
6.3 DELAYS AND CONTINUOUS ASSIGNMENTS.
6.4 ASSIGNMENT TO VECTORS.
6.5 OPERATORS.
6.6 ADDITIONAL EXAMPLES.
6.7 EXERCISES.
7 BEHAVIORAL MODELING — 1.
7.1 INTRODUCTION.
7.2 OPERATIONS AND ASSIGNMENTS.0
7.3 FUNCTIONAL BIFURCATION.1
7.4 INITIAL CONSTRUCT.
7.5 ALWAYS CONSTRUCT.
7.6 EXAMPLES.
7.7 ASSIGNMENTS WITH DELAYS.
7.8 wait CONSTRUCT.
7.9 MULTIPLE ALWAYS BLOCKS.
7.10 DESIGNS AT BEHAVIORAL LEVEL.
7.11 BLOCKING AND NONBLOCKING ASSIGNMENTS.
7.12 THE case STATEMENT.
7.13 SIMULATION FLOW.
7.14 EXERCISES.
8 BEHAVIORAL MODELING II.
8.1 INTRODUCTION.
8.2 if AND if–else CONSTRUCTS.
8.3 assign–deassign CONSTRUCT.
8.4 repeat CONSTRUCT.
8.5 for LOOP.
8.6 THE disable CONSTRUCT.
8.7 while LOOP.
8.8 forever LOOP.
8.9 PARALLEL BLOCKS.
8.10 force–release CONSTRUCT.
8.11 EVENT.
8.12 EXERCISES.
9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES.
9.1 INTRODUCTIUON.
9.2 FUNCTION.
9.3 TASKS.
9.4 USER-DEFINED PRIMITIVES (UDP).2
9.5 EXERCISES.
10 SWITCH LEVEL MODELING 305
10.1 INTRODUCTION.
10.2 BASIC TRANSISTOR SWITCHES.5
10.3 CMOS SWITCH.
10.4 BIDIRECTIONAL GATES.
10.5 TIME DELAYS WITH SWITCH PRIMITIVES.
10.6 INSTANTIATIONS WITH STRENGTHS AND DELAYS.
10.7 STRENGTH CONTENTION WITH TRIREG NETS.
10.8 EXERCISES.
11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES 339
11.1 INTRODUCTION.
11.2 PARAMETERS.9
11.3 PATH DELAYS.
11.4 MODULE PARAMETERS.
11.5 SYSTEM TASKS AND FUNCTIONS.
11.6 FILE-BASED TASKS AND FUNCTIONS.
11.7 COMPILER DIRECTIVES.
11.8 HIERARCHICAL ACCESS.
11.9 GENERAL OBSERVATIONS.
11.10 EXERCISES.
12 QUEUES, PLAS, AND FSMS.
12.1 INTRODUCTION.
12.2 QUEUES.
12.3 PROGRAMMABLE LOGIC DEVICES (PLDs).
12.4 DESIGN OF FINITE STATE MACHINES.
12.5 EXERCISES.
APPENDIX A (Keywords and Their Significance).
APPENDIX B (Truth Tables of Gates and Switches).
REFERENCES.
INDEX.
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