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Embedded SoPC Design with Nios II Processor and VHDL Examples

ISBN: 978-1-118-00888-1
736 pages
September 2011
Embedded SoPC Design with Nios II Processor and VHDL Examples (111800888X) cover image
The book is divided into four major parts. Part I covers HDL constructs and synthesis of basic digital circuits. Part II provides an overview of embedded software development with the emphasis on low-level I/O access and drivers. Part III demonstrates the design and development of hardware and software for several complex I/O peripherals, including PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card. Part IV provides three case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a Mandelbrot set fractal circuit, and an audio synthesizer based on DDFS (direct digital frequency synthesis) methodology.

The book utilizes FPGA devices, Nios II soft-core processor, and development platform from Altera Co., which is one of the two main FPGA manufactures. Altera has a generous university program that provides free software and discounted prototyping boards for educational institutions (details at http://www.altera.com/university). The two main educational prototyping boards are known as DE1 ($99) and DE2 ($269). All experiments can be implemented and tested with these boards. A board combined with this book becomes a “turn-key” solution for the SoPC design experiments and projects. Most HDL and C codes in the book are device independent and can be adapted by other prototyping boards as long as a board has similar I/O configuration.

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Preface.

Acknowledgments.

1. Ovweview of Embedded System.

Part I. Basic Digital Circuits Development.

2. Gate-level Combinational Circuit.

3. Overview of FPGA and EDA Software.

4. RT-level Combinational Circuit.

5. Regular Sequential Circuit.

6. FSM.

7. FSMD.

Part II. Basic NIOS II Software Development.

8. Nios II Processor Overview.

9. Nios II System Derivation and Low-Level Access.

10. Predesigned Nios II I/O Peripherals.

11. Predesigned Nios II I/O Drivers and HAL API.

12. Interrupt and ISR.

Part III. Custom I/O Peripheral Development.

13. Custom I/O Peripheral with PIO Cores.

14. Avalon Interconnect and SOPC Component.

15. SRAM and SDRAM Controllers.

16. PS2 Keyboard and Mouse.

17. VGA Controller.

18. Audio Codec Controller.

19. SD Card Controller.

IV. Hardware Accelerator Case Studies.

20. GCD Accelerator.

21. Mandelbrot Set Fractal Accelerator.

22. Direct Digital Frequency Synthesis.

References.

Topic Index. 

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Dr. Pong P. Chu is an Associate Professor in the Department of Electrical and Computer Engineering at Cleveland State University in Ohio. He obtained a BS degree from National Chiao Tung University, Taiwan, and a PhD from Iowa State University. He has taught undergraduate- and graduate-level digital systems and computer architecture courses for more than a decade and has received instructional grants from the National Science Foundation and Cleveland State University.
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