CMOS Sigma-Delta Converters: Practical Design Guide
March 2013, Wiley-IEEE Press
A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance.
This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations − going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues – from high-level behavioural modelling in MATLAB/SIMULINK, to circuit-level implementation in Cadence Design FrameWork II. As well as being a comprehensive reference to the theory, the book is also unique in that it gives special importance on practical issues, giving a detailed description of the different steps that constitute the whole design flow of sigma-delta ADCs.
The book begins with an introductory survey of sigma-delta modulators, their fundamentals architectures and synthesis methods covered in Chapter 1. In Chapter 2, the effect of main circuit error mechanisms is analysed, providing the necessary understanding of the main practical issues affecting the performance of sigma-delta modulators. The knowledge derived from the first two chapters is presented in the book as an essential part of the systematic top-down/bottom-up synthesis methodology of sigma-delta modulators described in Chapter 3, where a time-domain behavioural simulator named SIMSIDES is described and applied to the high-level design and verification of sigma-delta ADCs. Chapter 4 moves farther down from system-level to the circuit and physical level, providing a number of design recommendations and practical recipes to complete the design flow of sigma-delta modulators. To conclude the book, Chapter 5 gives an overview of the state-of-the-art sigma-delta ADCs, which are exhaustively analysed in order to extract practical design guidelines and to identify the incoming trends, design challenges as well as practical solutions proposed by cutting-edge designs.
- Offers a complete survey of sigma-delta modulator architectures from fundamentals to state-of-the art topologies, considering both switched-capacitor and continuous-time circuit implementations
- Gives a systematic analysis and practical design guide of sigma-delta modulators, from a top-down/bottom-up perspective, including mathematical models and analytical procedures, behavioural modeling in MATLAB/SIMULINK, macromodeling, and circuit-level implementation in Cadence Design FrameWork II, chip prototyping, and experimental characterization.
- Systematic compilation of cutting-edge sigma-delta modulators
- Complete description of SIMSIDES, a time-domain behavioural simulator implemented in MATLAB/SIMULINK
- Plenty of examples, case studies, and simulation test benches, covering the different stages of the design flow of sigma-delta modulators
- A number of electronic resources, including SIMSIDES, the statistical data used in the state-of-the-art survey, as well as many design examples and test benches are hosted on a companion website
Essential reading for Researchers and electronics engineering practitioners interested in the design of high-performance data converters integrated in nanometer CMOS technologies; mixed-signal designers.
List of Abbreviations xvii
1 Introduction to ΣΔ Modulators: Basic Concepts and Fundamentals 1
1.1 Basics of A/D Conversion 2
1.2 Basics of Sigma-Delta Modulators 8
1.3 Classification of ΣΔ Modulators 15
1.4 Single-Loop ΣΔ Modulators 16
1.5 Cascade ΣΔ Modulators 24
1.6 Multibit ΣΔ Modulators 29
1.7 Band-Pass ΣΔ Modulators 36
1.8 Continuous-Time ΣΔ Modulators 41
1.9 Summary 49
2 Circuits and Errors: Systematic Analysis and Practical Design Issues 54
2.1 Nonidealities in Switched-Capacitor ΣΔ Modulators 55
2.2 Finite Amplifier Gain in SC-ΣΔMs 56
2.3 Capacitor Mismatch in SC-ΣΔMs 60
2.4 Integrator Settling Error in SC-ΣΔMs 62
2.5 Circuit Noise in SC-ΣΔMs 71
2.6 Clock Jitter in SC-ΣΔMs 75
2.7 Sources of Distortion in SC-ΣΔMs 76
2.8 Nonidealities in Continuous-Time ΣΔ Modulators 80
2.9 Clock Jitter in CT-ΣΔMs 81
2.10 Excess Loop Delay in CT-ΣΔMs 85
2.11 Quantizer Metastability in CT-ΣΔMs 88
2.12 Finite Amplifier Gain in CT-ΣΔMs 89
2.13 Time-Constant Error in CT-ΣΔMs 92
2.14 Finite Integrator Dynamics in CT-ΣΔMs 94
2.15 Circuit Noise in CT-ΣΔMs 95
2.16 Sources of Distortion in CT-ΣΔMs 97
2.17 Case Study: High-Level Sizing of a ΣΔM 99
2.18 Summary 107
3 Behavioral Modeling and High-Level Simulation 110
3.1 Systematic Design Methodology of ΣΔ Modulators 110
3.2 Simulation Approaches for the High-Level Evaluation of ΣΔMs 113
3.3 Implementing ΣΔM Behavioral Models 118
3.4 Efficient Behavioral Modeling of ΣΔM Building Blocks using C-MEX S-Functions 134
3.5 SIMSIDES: A SIMULINK-Based Behavioral Simulator for ΣΔMs 159
3.6 Using SIMSIDES for the High-Level Sizing and Verification of ΣΔMs 167
3.7 Summary 183
4 Circuit-Level Design, Implementation, and Verification 186
4.1 Macromodeling ΣΔMs 186
4.2 Including Noise in Transient Electrical Simulations of ΣΔMs 199
4.3 Processing ΣΔM Output Results of Electrical Simulations 208
4.4 Design Considerations and Simulation Test Benches of ΣΔM Basic Building Blocks 213
4.5 Auxiliary ΣΔM Building Blocks 250
4.6 Layout Design, Floorplanning, and Practical Issues 257
4.7 Chip Package, Test PCB, and Experimental Set-Up 263
4.8 Summary 270
5 Frontiers of ΣΔ Modulators: Trends and Challenges 273
5.1 Overview of the State of the Art on ΣΔMs 274
5.2 Empirical and Statistical Analysis of State-of-the-Art ΣΔMs 291
5.3 Cutting-Edge ΣΔM Architectures and Techniques 300
5.4 Classification of State-of-the-Art References 319
5.5 Summary 319
A SIMSIDES User Guide 334
A.1 Getting Started: Installing and Running SIMSIDES 334
A.2 Building and Editing ΣΔM Architectures in SIMSIDES 335
A.3 Analyzing ΣΔMs in SIMSIDES 337
A.4 Example 345
A.5 Getting Help 354
B SIMSIDES Block Libraries and Models 355
B.1 Overview of SIMSIDES Libraries 355
B.2 Ideal Libraries 355
B.3 Real SC Building-Block Libraries 361
B.4 Real SI Building-Block Libraries 364
B.5 Real CT Building-Block Libraries 371
B.6 Real Quantizers and Comparators 382
B.7 Real D/A Converters 382
B.8 Auxiliary Blocks 384
José M. de la Rosa, IEEE Senior Member, received the M.S. degree in Physics in 1993 and the Ph.D. degree in Microelectronics in 2000, both from the University of Seville, Spain. Since 1993 he has been working at the Institute of Microelectronics of Seville (IMSE), which is in turn part of the Spanish Microelectronics Center (CNM) of the Spanish National Research Council (CSIC). He is also with the Department of Electronics and Electromagnetism of the University of Seville, where he is currently an Associate Professor.
His main research interests are in the field of analog and mixed-signal integrated circuits, especially high-performance data converters, including analysis, behavioral modeling, design and design automation of such circuits. In these topics, Dr. de la Rosa has participated in a number of National and European research and industrial projects, and has co-authored more than 170 international peer-reviewed publications, including journal and conference papers, book chapters and the books Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips (Kluwer, 2002), CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design (Springer, 2006) and Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio (Springer, 2011).
Dr. de la Rosa is a member of the Analog Signal Processing Technical Committee of the IEEE Circuits and Systems Society. He serves as Associate Editor for IEEE Transactions on Circuits and Systems I: Regular Papers. He has also served and is currently serving as a review committee member of IEEE ISCAS conference. He participated and is currently participating in the organizing and technical committees of diverse international conferences, among others IEEE MWSCAS, IEEE ICECS, IEEE LASCAS, IFIP/IEEE VLSI-SoC and DATE. He served as TPC co-chair of IEEE MWSCAS 2012 and IEEE ICECS 2012.
Rocío del Río Fernández received the M.S. degree in 1996 in Electronic Physics and the Ph.D. degree in 2004, both from the University of Seville, Spain. She joined the Department of Electronics and Electromagnetism of the University of Seville in 1995, where she is an Associate Professor. She is also since 1995 at the Institute of Microelectronics of Seville IMSE-CNM (CSIC / University of Seville), where she works in the group of “Analog and Mixed-Signal Microelectronics”.
Her main areas of interest are in the field of analog-to-digital converters (especially sigma-delta ADCs), including analysis, behavioral modeling, and design automation. She has participated in diverse National and European R&D projects and has co-authored more than 90 international publications, including journal and conference papers, and books and book chapters.
Dr. del Río has co-authored the books CMOS Cascade Sigma-Delta Modulators for Sensor and Telecom: Error Analysis and Practical Design (Springer, 2006) and Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio (Springer, 2011).