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ESD: Circuits and Devices, 2nd Edition

ISBN: 978-1-118-95446-1
544 pages
June 2015
ESD: Circuits and Devices, 2nd Edition (1118954467) cover image

Description

ESD: Circuits and Devices 2nd Edition provides a clear picture of layout and design of digital, analog, radio frequency (RF) and power applications for protection from electrostatic discharge (ESD), electrical overstress (EOS), and latchup phenomena from a generalist perspective and design synthesis practices providing optimum solutions in advanced technologies.

New features in the 2nd edition:

  • Expanded treatment of ESD and analog design of passive devices of resistors, capacitors, inductors, and active devices of diodes, bipolar junction transistors, MOSFETs, and FINFETs.
  • Increased focus on ESD power clamps for power rails for CMOS, Bipolar, and BiCMOS.
  • Co-synthesizing of semiconductor chip architecture and floor planning with ESD design practices for analog, and mixed signal applications
  • Illustrates the influence of analog design practices on ESD design circuitry, from integration, synthesis and layout, to symmetry, matching, inter-digitation, and common centroid techniques.
  • Increased emphasis on system-level testing conforming to IEC 61000-4-2 and IEC 61000-4-5.
  • Improved coverage of low-capacitance ESD, scaling of devices and oxide scaling challenges.

ESD: Circuits and Devices 2nd Edition is an essential reference to ESD, circuit & semiconductor engineers and quality, reliability &analysis engineers. It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, microelectronics and IC design.

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Table of Contents

About the Author xix

Preface xxi

Acknowledgments xxv

1 Electrostatic Discharge 1

1.1 Electricity and Electrostatic Discharge 1

1.2 Fundamental Concepts of ESD Design 11

1.3 ESD, EOS, EMI, Electromagnetic Compatibility, and Latchup 18

1.4 ESD Models 19

1.5 ESD and System-Level Test Models 28

1.6 Time Constants 39

1.7 Capacitance, Resistance, and Inductance and ESD 59

1.8 Rules of Thumb and ESD 62

1.9 ESD Scaling 63

1.10 Lumped versus Distributed Analysis and ESD 65

1.11 ESD Metrics: Chip-Level ESD Metrics and Figures of Merit 79

1.12 ESD Quality and Reliability Business Metrics 84

1.13 Twelve Steps to Building an ESD Strategy 85

1.14 Summary and Closing Comments 86

Problems 87

References 87

2 Design Synthesis 94

2.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection 94

2.2 Electrical and Spatial Connectivity 95

2.3 ESD, Latchup, and Noise 96

2.4 Interface Circuits and ESD Elements 98

2.5 ESD Power Clamp Networks 101

2.6 ESD Rail-to-Rail Networks 105

2.7 Guard Rings 109

2.8 Pads, Floating Pads, and No-connect Pads 111

2.9 Structures under Bond Pads 112

2.10 Mixed Signal Architecture: CMOS 112

2.11 MS Architecture: Digital, Analog, and RF Architecture 116

2.12 Digital-to-Analog Interdomain Signal Line Failures 118

2.13 Summary and Closing Comments 124

Problems 124

References 125

3 MOSFET ESD Design 129

3.1 Basic ESD Design Concepts 129

3.2 ESD MOSFET Design: Channel Length 136

3.3 N-Channel MOSFET Design: Channel Width 143

3.4 ESD MOSFET Design: Contacts 144

3.5 ESD MOSFET Design: Metal Distribution 153

3.6 ESD MOSFET Design: Silicide Masking 165

3.7 ESD MOSFET Design: Series Cascode Configurations 170

3.8 ESD MOSFET Design: Multifinger MOSFET Design—Integration of Coupling and Ballasting Techniques 174

3.9 ESD MOSFET Design: Enclosed Drain Design Practice 181

3.10 ESD MOSFET Interconnect Ballasting Design 182

3.11 ESD MOSFET Design: Source and Drain Segmentation 184

3.12 MOSFET Design for Analog Applications 185

3.13 Summary and Closing Comments 187

Problems 187

References 188

4 ESD Design: Diode Design 191

4.1 ESD Diode Design: ESD Basics 191

4.2 ESD Diode Anode Design 194

4.3 ESD Diode Design: Interconnect Wiring 202

4.4 ESD Design: Polysilicon-Bound Diode Designs 210

4.5 N-Well Diode Design 213

4.6 N+/P Substrate Diode Design 216

4.7 ESD Design: Diode String Design 217

4.8 Triple-Well ESD Diode Design 231

4.9 Summary and Closing Comments 234

Problems 234

References 236

5 ESD Design: Passive Resistors 239

5.1 N-Well Resistors 239

5.2 N-Diffusion Resistor Design 248

5.3 P-Diffusion Resistor Design 252

5.4 BR 254

5.5 Summary and Closing Comments 268

Problems 268

References 270

6 Passives for Digital, Analog, and RF Applications 271

6.1 Analog Design Layout Revisited 271

6.2 Common Centroid Design 274

6.3 Interdigitation Design 275

6.4 Common Centroid and Interdigitation Design 276

6.5 Passive Element Design 277

6.6 Resistor Element Design 277

6.7 Capacitor Element Design 283

6.8 Inductor Element Design 283

6.9 Summary and Closing Comments 286

Problems 286

References 286

7 Off-Chip Drivers and ESD 288

7.1 Off-chip Drivers 288

7.2 OCDs: MVI 297

7.3 OCDs: Self-Bias Well OCD Networks 297

7.4 Programmable Impedance OCD Network 302

7.5 OCDs: Universal OCDs 305

7.6 OCDs: Gate-Array OCD Design 306

7.7 OCDs: Gate-Modulated Networks 309

7.8 OCDs ESD Design: Integration of Coupling and Ballasting Techniques 311

7.9 Substrate-Modulated Resistor-Ballasted MOSFET 315

7.10 Summary and Closing Comments 317

Problems 318

References 319

8 Receiver Circuits 322

8.1 Receivers and ESD 322

8.2 Receivers and ESD 324

8.3 Receivers and Receiver Evolution 327

8.4 Receiver Circuits with Pseudozero VT Half-Pass TG 337

8.5 Receiver with ZVT TG 339

8.6 Receiver Circuits with Bleed Transistors 342

8.7 Receiver Circuits with Test Functions 343

8.8 Receiver with Schmitt Trigger Feedback Network 344

8.9 Bipolar Transistor Receivers 347

8.10 Differential Receivers 349

8.11 CMOS Differential Receiver with Analog Layout Concepts 355

8.12 Summary and Closing Comments 363

Problems 364

References 366

9 Silicon on Insulator (SOI) ESD Design 368

9.1 Silicon on Insulator ESD Design Concepts 368

9.2 SOI Design MOSFET with Body Contact: T-Shape Layout Style 372

9.3 SOI Lateral Diode Structure 375

9.4 SOI BR Elements 380

9.5 Dynamic Threshold SOI MOSFET 381

9.6 SOI Dual-Gate MOSFET 384

9.7 SOI ESD Design: Mixed Voltage T-Shape Layout Style 384

9.8 SOI ESD Design: Mixed Voltage Diode Strings 384

9.9 SOI ESD Design: Double-Diode Network 385

9.10 Bulk to SOI ESD Design Remapping 387

9.11 SOI ESD Design in MVI Environments 391

9.12 Comparison of Bulk to SOI ESD Results 393

9.13 SOI ESD Design with Aluminum Interconnects 394

9.14 SOI ESD Design with Copper Interconnects 395

9.15 SOI ESD Design with Gate Circuitry 397

9.16 SOI FinFET Structure 399

9.17 Summary and Closing Comments 403

Problems 403

References 405

10 ESD Circuits: BiCMOS 408

10.1 Bipolar ESD Input Circuits 408

10.2 Diode-Configured Bipolar ESD Input Circuits 412

10.3 Bipolar ESD Input Circuits: Voltage-Triggered Elements 413

10.4 BiCMOS Mixed Signal Designs 437

10.5 Summary and Closing Comments 437

Problems 437

References 438

11 ESD Power Clamps 442

11.1 ESD Power Clamp Design Practices 442

11.2 Design Synthesis of ESD Power Clamps Trigger Networks 446

11.3 Design Synthesis of ESD Power Clamp: The ESD Power Clamp Shunting Element 449

11.4 ESD Power Clamp Issues 452

11.5 ESD Power Clamp Design 453

11.6 Master/Slave ESD Power Clamp Systems 458

11.7 Series-Stacked RC-Triggered ESD Power Clamps 460

11.8 ESD Power Clamps: Triple-Well Series Diodes as Core Clamps 460

11.9 Summary and Closing Comments 464

Problems 465

References 466

12 Bipolar ESD Power Clamps 468

12.1 Bipolar ESD Power Clamps 468

12.2 Bipolar Voltage-Triggered ESD Power Clamps 468

12.3 ESD Power Clamp Design Synthesis: Bipolar ESD Power Clamps 473

12.4 Mixed Voltage Interface Forward-Bias Voltage and BVCEO Breakdown Synthesized Bipolar ESD Power Clamps 476

12.5 Ultralow-Voltage Forward-Biased Voltage-Trigger BiCMOS ESD Power Clamp 480

12.6 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance Triggered 485

12.7 Summary and Closing Comments 485

Problems 486

References 487

13 Silicon-Controlled Rectifier Power Clamps 489

13.1 ESD Silicon-Controlled Rectifier Circuits 489

13.2 Lateral Diffused MOS Circuits 492

13.3 DeMOS Circuits 496

13.4 Ultrahigh-Voltage LDMOS (UHV-LDMOS) Circuits 497

13.5 Summary and Closing Comments 497

Problems 501

References 501

Glossary of Terms 504

Standards 509

Index 

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Author Information

Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.”  Voldman was a member of the semiconductor development of IBM, Qimonda, and Intersil and worked as a full time consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC) and a consultant on latchup, for the Samsung Electronics Corporation. He initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally reaching over 40  universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, China and Senegal. He is a recipient of 252 issued US patents and has written over 150 technical papers. He has served as an expert witness in patent litigation; and has also founded a limited liability corporation (LLC) consulting business supporting patents, patent writing and patent litigation. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents.

Dr. Voldman is an author of the  book series including  ESD: Physics and Devices, ESD: Circuits and Devices, 2nd Edition of ESD: Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, Latchup, ESD: Failure Mechanisms and Models,  ESD: Design and Synthesis, ESD Basics: From Semiconductor Manufacturing to Product Use, and Electrical Overstress (EOS): Devices, Circuits and Systems, ESD: Analog Circuits and Design,, as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design andNanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. In addition, the International Chinese editions of booksare also released.

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