Understanding DeltaSigma Data Converters, 2nd EditionISBN: 9781119258278
584 pages
January 2017, WileyIEEE Press

Description
This new edition introduces operation and design techniques for SigmaDelta converters in physical and conceptual terms, and includes chapters which explore developments in the field over the last decade
 Includes information on MASH architectures, digitaltoanalog converter (DAC) mismatch and mismatch shaping
 Investigates new topics including continuoustime ΔΣ analogtodigital converters (ADCs) principles and designs, circuit design for both continuoustime and discretetime ΔΣ ADCs, decimation and interpolation filters, and incremental ADCs
 Provides emphasis on practical design issues for industry professionals
Table of Contents
1 The Magic of DeltaSigma Modulation 1
1.1 The Need for Oversampling Converters 1
1.2 Nyquist and Oversampling Conversion by Example 3
1.3 HigherOrder SingleStage NoiseShaping Modulators 11
1.4 MultiStage and MultiQuantizer DeltaSigma Modulators 12
1.5 Mismatch Shaping in MultiBit DeltaSigma Modulators 14
1.6 ContinuousTime DeltaSigma Modulation 15
1.7 Bandpass DeltaSigma Modulators 17
1.8 Incremental DeltaSigma Converters 18
1.9 DeltaSigma DigitaltoAnalog Converters 18
1.10 Decimation and Interpolation 19
1.11 Specifications and Figures of Merit 19
1.12 Early History, Performance, and Architectural Trends 21
References 25
2 Sampling, Oversampling, and NoiseShaping 27
2.1 A Review of Sampling 28
2.2 Quantization 30
2.3 Quantization Noise Reduction by Oversampling 39
2.4 NoiseShaping 42
2.5 Nonlinear Aspects of the FirstOrder DeltaSigma Modulator 52
2.6 MOD1 with DC Excitation 54
2.7 Alternative Architectures: The ErrorFeedback Structure 60
2.8 The Road Ahead 60
References 61
3 SecondOrder DeltaSigma Modulation 63
3.1 Simulation of MOD2 67
3.2 Nonlinear Effects in MOD2 70
3.3 Stability of MOD2 73
3.4 Alternative SecondOrder Modulator Structures 77
3.5 Generalized SecondOrder Structures 80
3.6 Conclusions 82
References 82
4 HighOrder DeltaSigma Modulators 83
4.1 SignalDependent Stability of DeltaSigma Modulators 85
4.2 Improving MSA in HighOrder DeltaSigma Converters 92
4.3 Systematic NTF Design 95
4.4 Noise Transfer Functions with Optimally Spread Zeros 97
4.5 Fundamental Aspects of Noise Transfer Functions 98
4.6 HighOrder SingleBit DeltaSigma Data Converters 100
4.7 Loop Filter Topologies for DiscreteTime DeltaSigma Converters 104
4.8 StateSpace Description of DeltaSigma Loops 114
4.9 Conclusions 115
References 115
5 MultiStage and MultiQuantizer DeltaSigma Modulators 117
5.1 MultiStage Modulators 117
5.2 Cascade (MASH) Modulators 120
5.3 Noise Leakage in Cascade Modulators 123
5.4 The SturdyMASH Architecture 126
5.5 NoiseCoupled Architectures 128
5.6 CrossCoupled Architectures 131
5.7 Conclusions 131
References 133
6 MismatchShaping 135
6.1 The Mismatch Problem 135
6.2 Random Selection and Rotation 136
6.3 Implementation of Rotation 141
6.4 Alternative MismatchShaping Topologies 145
6.5 HighOrder MismatchShaping 151
6.6 Generalizations 156
6.7 TransitionError Shaping 158
6.8 Conclusions 162
References 162
7 Circuit Design for DiscreteTime DeltaSigma ADCs 165
7.1 SCMOD2: A SecondOrder SwitchedCapacitor ADC 165
7.2 HighLevel Design 166
7.3 SwitchedCapacitor Integrator 168
7.4 Capacitor Sizing 174
7.5 Initial Verification 176
7.6 Amplifier Design 178
7.7 Intermediate Verification 186
7.8 Switch Design 191
7.9 Comparator Design 191
7.10 Clocking 195
7.11 FullSystem Verification 197
7.12 HighOrder Modulators 201
7.13 MultiBit Quantization 203
7.14 Switch Design Revisited 207
7.15 Double Sampling 209
7.16 GainBoosting and GainSquaring 211
7.17 SplitSteering and Amplifier Stacking 212
7.18 Noise in SwitchedCapacitor Circuits 217
7.19 Conclusions 221
References 221
8 ContinuousTime DeltaSigma Modulation 223
8.1 CTMOD1 224
8.2 STF of CTMOD1 230
8.3 SecondOrder ContinuousTime DeltaSigma Modulation 234
8.4 HighOrder ContinuousTime DeltaSigma Modulators 239
8.5 LoopFilter Topologies 246
8.6 ContinuousTime DeltaSigma Modulators with Complex NTF Zeros 249
8.7 Modeling of ContinuousTime DeltaSigma Modulators for Simulation 250
8.8 DynamicRange Scaling 253
8.9 Design Example 255
8.10 Conclusions 258
References 258
9 Nonidealities in ContinuousTime DeltaSigma Modulators 259
9.1 Excess Loop Delay 259
9.2 TimeConstant Variations of the Loop Filter 271
9.3 Clock Jitter in DeltaSigma Modulators 273
9.4 Addressing Clock Jitter in ContinuousTime DeltaSigma Modulators 285
9.5 Mitigating Clock Jitter Using FIR Feedback 287
9.6 Comparator Metastability 293
9.7 Conclusions 298
References 298
10 Circuit Design for ContinuousTime DeltaSigma Modulators 301
10.1 Integrators 302
10.2 The MillerCompensated OTARC Integrator 305
10.3 The FeedforwardCompensated OTARC Integrator 306
10.4 Stability of Feedforward Amplifiers 309
10.5 Device Noise in ContinuousTime DeltaSigma Modulators 312
10.6 ADC Design 316
10.7 Feedback DAC Design 320
10.8 Systematic Design Centering 331
10.9 LoopFilter Nonlinearities in ContinuousTime DeltaSigma Modulators 338
10.10 Case Study of a 16Bit Audio ContinuousTime DeltaSigma Modulator346
10.11 Measurement Results 358
10.12 Summary 359
References 360
11 Bandpass and Quadrature DeltaSigma Modulation 363
11.1 The Need for Bandpass Conversion 363
11.2 System Overview 366
11.3 Bandpass NTFs 367
11.4 Architectures for Bandpass DeltaSigma Modulators 372
11.5 Bandpass Modulator Example 380
11.6 Quadrature Signals 391
11.7 Quadrature Modulation 396
11.8 Polyphase Signal Processing 402
11.9 Conclusions 404
References 405
12 Incremental AnalogtoDigital Converters 407
12.1 Motivation and TradeOffs 407
12.2 Analysis and Design of SingleStage IADCs 408
12.3 Digital Filter Design for SingleStage IADCs 411
12.4 MultipleStage IADCs and Extended Counting ADCs 415
12.5 IADC Design Examples 416
12.6 Conclusions 422
References 423
13 DeltaSigma DACs 425
13.1 System Architectures for DeltaSigma DACs 425
13.2 Loop Configurations for DeltaSigma DACs 427
13.3 DeltaSigma DACs Using MultiBit Internal DACs 431
13.4 Interpolation Filtering for DeltaSigma DACs 438
13.5 Analog PostFilters for DeltaSigma DACs 441
13.6 Conclusions 449
References 449
14 Interpolation and Decimation Filters 451
14.1 Interpolation Filtering 452
14.2 Example Interpolation Filter 456
14.3 Decimation Filtering 461
14.4 Example Decimation Filter 463
14.5 Halfband Filters 467
14.5.1 Saramäki Halfband Filter 469
14.6 Decimation for Bandpass DeltaSigma ADCs 471
14.7 Fractional Rate Conversion 472
14.8 Summary 480
References 480
A Spectral Estimation 483
A.1 Windowing 484
A.2 Scaling and Noise Bandwidth 488
A.3 Averaging 491
A.4 An Example 493
A.5 Mathematical Background 495
References 498
B The DeltaSigma Toolbox 499
C Linear Periodically TimeVarying Systems 539
C.1 Linearity and Time (In)variance 539
C.2 Linear TimeVarying Systems 541
C.3 Linear Periodically TimeVarying (LPTV) Systems 543
C.4 LPTV Systems with Sampled Outputs 547
References 559
Index 561
Author Information
Shanthi Pavan is a Professor of electrical engineering at the Indian Institute of Technology, India, and has been the EditorInChief of the IEEE Transactions on Circuits and Systems, and a Distinguished Lecturer of the IEEE Solid State Circuits Society. He is a Fellow of the Indian National Academy of Engineering.
Richard Schreier was a Division Fellow in Analog Devices Inc. and an Adjunct Professor at the University of Toronto, Canada, when he retired in 2016. From 19911997 he was a Professor at Oregon State University.He was named an IEEE Fellow in 2015.
Gabor Temes is a Distinguished Professor Emeritus of the University of California, and Professor in the School of Electrical Engineering and Computer Science at Oregon State University, USA. He is an IEEE Life Fellow and a member of the US National Academy of Engineering.