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Digital Design, 2E

March 2010, ©2011
Digital Design, 2E (EHEP001621) cover image

Description

"Thank you very much for this wonderful textbook. It is the best textbook I have ever seen. The students like it so much." --Mahamed G. H. Omran, PhD, Assistant Professor, Gulf University for Science & Technology, Kuwait

Unique with its RTL-early organization, Vahid's text supports instructors wishing to develop strong design skills in their students. The emergence of parallel processing, multicore processors and FPGAs are blurring the lines between hardware and software and fundamentally altering the way digital design and design logic should be taught. Vahid's RTL-early approach better assists students in grasping the essential design fundamentals before digging into specific details of design optimization.

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Table of Contents

Preface.

To Students About To Study Digital Design.

To Instructors of Digital Design.

How to Use This Book.

RTL-Focused Approach.

Traditional Approach with Some Reordering.

Traditional Approach.

Acknowledgements.

About the Cover.

About the Author.

Reviewers and Evaluators.

CHAPTER 1 Introduction.

1.1 Digital Systems in the World Around Us.

1.2 The World of Digital Systems.

1.3 Implementing Digital Systems: Microprocessors versus Digital Circuits.

1.4 About this Book.

1.5 Exercises.

CHAPTER 2 Combinational Logic Design.

2.1 Introduction.

2.2 Switches.

2.3 The CMOS Transistor.

2.4 Boolean Logic Gates—Building Blocks for Digital Circuits.

2.5 Boolean Algebra.

2.6 Representations of Boolean Functions.

2.7 Combinational Logic Design Process.

2.8 More Gates.

2.9 Decoders and Muxes.

2.10 Additional Considerations.

2.11 Combinational Logic Optimizations and Tradeoffs (See Section 6.2).

2.12 Combinational Logic Description Using Hardware Description Languages (See

Section 9.2).

2.13 Chapter Summary.

2.14 Exercises.

CHAPTER 3 Sequential Logic Design: Controllers.

3.1 Introduction.

3.2 Storing One Bit—Flip-Flops.

3.3 Finite-State Machines (FSMs).

3.4 Controller Design.

3.5 More on Flip-Flops and Controllers.

3.6 Sequential Logic Optimizations and Tradeoffs (See Section 6.3).

3.7 Sequential Logic Description Using.

3.8 Product Profile—Pacemaker.

3.9 Chapter Summary.

3.10 Exercises.

CHAPTER 4 Datapath Components.

4.1 Introduction.

4.2 Registers.

4.3 Adders.

4.4 Comparators.

4.5 Multiplier—Array-Style.

4.6 Subtractors and Signed Numbers.

4.7 Arithmetic-Logic Units—ALUs.

4.8 Shifters.

4.9 Counters and Timers.

4.10 Register Files.

4.11 Datapath Component Tradeoffs (See Section 6.4).

4.12 Datapath Component Description Using Hardware Description Languages (See Section 9.4).

4.13 Product Profile: An Ultrasound Machine.

4.14 Chapter Summary.

4.15 Exercises.

CHAPTER 5 Register-Transfer Level (RTL) Design.

5.1 Introduction.

5.2 High-Level State Machines.

5.3 RTL Design Process.

5.4 More RTL Design.

5.5 Determining Clock Frequency.

5.6 Behavioral-Level Design: C to Gates (Optional).

5.7 Memory Components.

5.8 Queues (FIFOs).

5.9 Multiple Processors.

5.10 Hierarchy—A Key Design Concept.

5.11 RTL Design Optimizations and Tradeoffs (See Section 6.5).

5.12 RTL Design Using Hardware Description Languages (See Section 9.5).

5.13 Product Profile: Cell Phone.

5.14 Chapter Summary.

5.15 Exercises.

CHAPTER 6 Optimizations and Tradeoffs.

6.1 Introduction.

6.2 Combinational Logic Optimizations and Tradeoffs.

6.3 Sequential Logic Optimizations and Tradeoffs.

6.4 Datapath Component Tradeoffs.

6.5 RTL Design Optimizations and Tradeoffs.

6.6 More on Optimizations and Tradeoffs.

6.7 Product Profile: Digital Video Player/Recorder.

6.8 Chapter Summary.

6.9 Exercises.

CHAPTER 7 Physical Implementation on ICs.

7.1 Introduction.

7.2 Manufactured IC Types.

7.3 Off-the-Shelf Programmable IC Type—FPGA.

7.4 Other Off-the-Shelf IC Types.

7.5 IC Tradeoffs, Trends, and Comparisons.

7.6 Product Profile: Giant LED-Based Video.

7.7 Chapter Summary.

7.8 Exercises.

CHAPTER 8 Programmable Processors.

8.1 Introduction.

8.2 Basic Architecture.

8.3 A Three-Instruction Programmable Processor.

8.4 A Six-Instruction Programmable Processor.

8.5 Example Assembly and Machine Programs

8.6 Further Extensions to the Programmable Processor.

8.7 Chapter Summary.

8.8 Exercises.

CHAPTER 9 Hardware Description Languages.

9.1 Introduction.

9.2 Combinational Logic Description Using Hardware Description Languages.

9.3 Sequential Logic Description Using Hardware Description Languages.

9.4 Datapath Component Description.

9.5 RTL Design Using Hardware Description Languages.

9.6 Chapter Summary.

9.7 Exercises.

APPENDIX A Boolean Algebras.

A.1 Boolean Algebra.

A.2 Switching Algebra.

A.3 Important Theorems in Boolean Algebra.

A.4 Other Examples of Boolean Algebras.

A.5 Further Readings.

APPENDIX B Additional Topics in Binary Number Systems.

B.1 Introduction.

B.2 Real Number Representation.

B.3 Fixed Point Arithmetic.

B.4 Floating Point Representation.

The IEEE 754-1985 Standard.

B.5 Exercises.

APPENDIX C Extended RTL Design Example.

C.1 Introduction.

C.2 Designing the Soda Dispenser Controller.

C.3 Understanding the Behavior of the Soda Dispenser Controller and Datapath.

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New To This Edition

  • New robust book companion site for students and instructors.
  • HDL supplements now available as print-on-demand or digital ebook.
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The Wiley Advantage

· Extensive use of examples. Basic ones teach new concepts, and applications?like pacemakers and cell phones?demonstrate relevance.

· HDL Neutral Synthesizable VHDL, Verilog, and SystemC coverage all appear in the last chapter, with subsections corresponding to earlier chapters, allowing early or late HDL introduction, without cluttering main concepts.

· Appropriate emphasis on RTL. Topic coverage naturally leads to register-transfer-level (RTL) design, which is covered substantially. Comparisons between custom digital circuit and microprocessor implementations provide a modern perspective.

· Modern coverage of optimization and tradeoffs. Tradeoffs are introduced alongside optimization, at all levels of abstraction (not just gate level), and cleanly distinguished from basic design.

· Bottom-up description of field-programmable gate arrays (FPGAs). FPGA coverage shows precisely how circuits can be mapped to lookup tables and switch matrices using bitstreams.

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Purchase Options
Hardcover   
Digital Design with RTL Design, VHDL, and Verilog, 2nd Edition
ISBN : 978-0-470-53108-2
594 pages
March 2010, ©2011
$239.95   BUY

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