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Design of High-Performance Microprocessor Circuits

Anantha Chandrakasan (Editor), William J. Bowhill (Editor), Frank Fox (Editor)
ISBN: 978-0-7803-6001-3
584 pages
October 2000, Wiley-IEEE Press
Design of High-Performance Microprocessor Circuits (078036001X) cover image


This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola.

Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth:

  • Architectural constraints of CMOS VLSI design
  • Technology scaling, low-power devices, SOI, and process variations
  • Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units
  • Latches, clocks and clock distribution, phase-locked and delay-locked loops
  • Register file, cache memory, and embedded DRAM design
  • High-speed signaling techniques and I/O design
  • ESD, electromigration, and hot-carrier reliability
  • CAD tools, including timing verification and the analysis of power distribution schemes
  • Test and testability

Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

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Table of Contents



Impact of Physical Technology on Architecture (John H. Edmondson).


CMOS Scaling and Issues in SUB-0.25µm Systems (Yuan Taur).

Techniques for Leakage Power Reduction (Vivek De, Yibin Ye, et al.).

Low-Voltage Technologies (Tadahiro Kuroda and Takayasu Sakurai).

SOI Technology and Circuits (Ghavam G. Shahidi, Fari Assaderaghi and Dimitri Antoniadis).

Models of Process Variations in Device and Interconnect (Duane Boning and Sani Nassif).


Basic Logic Families (Kerry Bernstein).

Issues in Dynamic Logic Design (Paul Gronowski).

Self-Timed Pipelines (Ted Williams).

High-Speed VLSI Arithmetic Units: Adders and Multipliers (Vojin G. Oklobdzija).


Clocked Storage Elements (Hamid Partovi).

Design of High-Speed CMOS PLLs and DLLs (John George Maneatis).

Clock Distribution (Daniel W. Bailey).


Register Files and Caches (Ronald Preston).

Embedded DRAM (Tadaaki Yamauchi and Michihiro Yamada).


Analyzing On-Chip Interconnect Effects (Noel Menezes and Lawrence Pileggi).

Techniques for Driving Interconnect (Shannon V. Morton).

I/O and ESD Circuit Design (Stephen C. Thierauf and Warren R. Anderson).

High-Speed Electrical Signaling (Stefanos Sidropoulos, Chih-Kong Ken Yang, and Mark Horowitz).


Electromigration Reliability (J. Joseph Clement).

Hot Carrier Reliability (Kaizad Mistry).


Overview of Computer-Aided Design Tools (Yao-Tsung Yen).

Timing Verification (Victor Peng).

Design and Analysis of Power Distribution Networks (David Blaauw, Rajendran Panda, and Rajat Chaudhry).

Testing of High-Performance Processors (Dilip K. Bhavsar).

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Author Information

About the Editors...
Anantha Chandrakasan is an associate professor of electrical engineering and computer science at the Massachusetts Institute of Technology. Dr. Chandrakasan has received numerous awards and has served on the technical program committees of various IEEE and ACM conferences. His research interests include the energy efficient implementation of DSPs, wireless microsensor networks, and CAD tools for VLSI.
William J. Bowhill is a principal member of technical staff in Compaq Computer Corporation's Alpha Development Group (formerly Digital Equipment Corp.). He has contributed to many VAX and Alpha microprocessor designs. Prior to joining Digital in 1985, he designed telecommunication chips for Standard Telecommunication Research Laboratories in England. He has a B.Eng. from Liverpool University.
Frank Fox (Thomas F. Fox) has been a vice president at Rambus Inc., since 1998. Previously, he worked for Digital Equipment Corporation, where he led the fifth generation Alpha microprocessor design team. During his fourteen years at Digital, he designed many microprocessors and consulted on CMOS technology and CAD tools. Dr. Fox has a B.E. from University College Cork, National University of Ireland and a Ph.D. from Trinity College, Dublin University.
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