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Design of High-Performance Microprocessor Circuits

Design of High-Performance Microprocessor Circuits

Anantha Chandrakasan (Editor), William J. Bowhill (Editor), Frank Fox (Editor)

ISBN: 978-0-780-36001-3

Oct 2000, Wiley-IEEE Press

584 pages

Select type: Hardcover

In Stock

$252.00

Description

This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola.

Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth:

  • Architectural constraints of CMOS VLSI design
  • Technology scaling, low-power devices, SOI, and process variations
  • Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units
  • Latches, clocks and clock distribution, phase-locked and delay-locked loops
  • Register file, cache memory, and embedded DRAM design
  • High-speed signaling techniques and I/O design
  • ESD, electromigration, and hot-carrier reliability
  • CAD tools, including timing verification and the analysis of power distribution schemes
  • Test and testability

Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

Preface.

OVERVIEW.

Impact of Physical Technology on Architecture (John H. Edmondson).

TECHNOLOGY ISSUES.

CMOS Scaling and Issues in SUB-0.25µm Systems (Yuan Taur).

Techniques for Leakage Power Reduction (Vivek De, Yibin Ye, et al.).

Low-Voltage Technologies (Tadahiro Kuroda and Takayasu Sakurai).

SOI Technology and Circuits (Ghavam G. Shahidi, Fari Assaderaghi and Dimitri Antoniadis).

Models of Process Variations in Device and Interconnect (Duane Boning and Sani Nassif).

CIRCUIT STYLES FOR LOGIC.

Basic Logic Families (Kerry Bernstein).

Issues in Dynamic Logic Design (Paul Gronowski).

Self-Timed Pipelines (Ted Williams).

High-Speed VLSI Arithmetic Units: Adders and Multipliers (Vojin G. Oklobdzija).

CLOCKING.

Clocked Storage Elements (Hamid Partovi).

Design of High-Speed CMOS PLLs and DLLs (John George Maneatis).

Clock Distribution (Daniel W. Bailey).

MEMORY SYSTEM DESIGN.

Register Files and Caches (Ronald Preston).

Embedded DRAM (Tadaaki Yamauchi and Michihiro Yamada).

INTERCONNECT AND I/O.

Analyzing On-Chip Interconnect Effects (Noel Menezes and Lawrence Pileggi).

Techniques for Driving Interconnect (Shannon V. Morton).

I/O and ESD Circuit Design (Stephen C. Thierauf and Warren R. Anderson).

High-Speed Electrical Signaling (Stefanos Sidropoulos, Chih-Kong Ken Yang, and Mark Horowitz).

RELIABILITY.

Electromigration Reliability (J. Joseph Clement).

Hot Carrier Reliability (Kaizad Mistry).

CAD TOOLS AND TEST.

Overview of Computer-Aided Design Tools (Yao-Tsung Yen).

Timing Verification (Victor Peng).

Design and Analysis of Power Distribution Networks (David Blaauw, Rajendran Panda, and Rajat Chaudhry).

Testing of High-Performance Processors (Dilip K. Bhavsar).

Index.