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Sigma-Delta Converters: Practical Design Guide, 2nd Edition

Sigma-Delta Converters: Practical Design Guide, 2nd Edition

Jose M. de la Rosa

ISBN: 978-1-119-27576-3

Sep 2018, Wiley-IEEE Press

568 pages

$120.99

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Description

Thoroughly revised and expanded to help readers systematically increase their knowledge and insight about Sigma-Delta Modulators

Sigma-Delta Modulators (SDMs) have become one of the best choices for the implementation of analog/digital interfaces of electronic systems integrated in CMOS technologies. Compared to other kinds of Analog-to-Digital Converters (ADCs), Σ∆Ms cover one of the widest conversion regions of the resolution-versus-bandwidth plane, being the most efficient solution to digitize signals in an increasingly number of applications, which span from high-resolution low-bandwidth digital audio, sensor interfaces, and instrumentation, to ultra-low power biomedical systems and medium-resolution broadband wireless communications.

Following the spirit of its first edition, Sigma-Delta Converters: Practical Design Guide, 2nd Edition takes a comprehensive look at SDMs, their diverse types of architectures, circuit techniques, analysis synthesis methods, and CAD tools, as well as their practical design considerations. It compiles and updates the current research reported on the topic, and explains the multiple trade-offs involved in the whole design flow of Sigma-Delta Modulators—from specifications to chip implementation and characterization. The book follows a top-down approach in order to provide readers with the necessary understanding about recent advances, trends, and challenges in state-of-the-art Σ∆Ms. It makes more emphasis on two key points, which were not treated so deeply in the first edition:

  • It includes a more detailed explanation of Σ∆Ms implemented using Continuous-Time (CT) circuits, going from system-level synthesis to practical circuit limitations.
  • It provides more practical case studies and applications, as well as a deeper description of the synthesis methodologies and CAD tools employed in the design of Σ∆ converters.

Sigma-Delta Converters: Practical Design Guide, 2nd Edition serves as an excellent textbook for undergraduate and graduate students in electrical engineering as well as design engineers working on SD data-converters, who are looking for a uniform and self-contained reference in this hot topic. With this goal in mind, and based on the feedback received from readers, the contents have been revised and structured to make this new edition a unique monograph written in a didactical, pedagogical, and intuitive style. 

List of Abbreviations xvii

Preface xxi

Acknowledgements xxix

1 Introduction to __ Modulators: Fundaments, Basic Architecture and Performance Metrics 1

1.1 Basics of Analog-to-Digital Conversion 1

1.1.1 Sampling 3

1.1.2 Quantization 4

1.1.3 Quantization White Noise Model 6

1.1.4 Noise Shaping 9

1.2 Sigma-Delta Modulation 11

1.2.1 From Noise-Shaped Systems to __ Modulators 11

1.2.2 Performance Metrics of __Ms 12

1.3 The First-Order __ Modulator 15

1.4 Performance Enhancement and Taxonomy of __Ms 18

1.4.1 __M System-Level Design Parameters and Strategies 19

1.4.2 Classification of __Ms 20

1.5 Putting All Pieces Together: From __Ms to __ ADCs 21

1.5.1 Some Words About __ Decimators 22

1.6 __ DACs 25

1.6.1 System Design Trade-offs and Signal Processing in __ DACs 26

1.6.2 Implementation of Digital __Ms used in DACs 28

1.7 Summary 30

2 Taxonomy of __ Architectures 33

2.1 Second-Order __ Modulators 33

2.1.1 Alternative Representations of Second-Order __Ms 35

2.1.2 Second-Order __M with Unity STF 39

2.2 High-Order Single-Loop __Ms 40

2.3 Cascade __ Modulators 45

2.3.1 SMASH __M Architectures 49

2.4 Multibit __ Modulators 54

2.4.1 Influence of Multibit DAC Errors 54

2.4.2 Dynamic Element Matching Techniques 56

2.4.3 Dual Quantization 59

2.5 Band-Pass __ Modulators 61

2.5.1 Quadrature BP-__Ms 63

2.5.2 The z ! z LP–BP Transformation 63

2.5.3 BP-__Ms with Optimized NTF 66

2.5.4 Time-Interleaved and Polyphase BP-__Ms 69

2.6 Continuous-Time __ Modulators: Architecture and Basic Concepts 72

2.6.1 An Intuitive Analysis of CT-__Ms 74

2.6.2 Some Words about Alias Rejection in CT-__Ms 77

2.7 DT–CT Transformation of __Ms 79

2.7.1 The Impulse-Invariant Transformation 79

2.7.2 DT–CT Transformation of a Second-Order __M 80

2.8 Direct Synthesis of CT-__Ms 84

2.9 Summary 86

3 Circuit Errors in Switched-Capacitor __ Modulators 93

3.1 Overview of Nonidealities in Switched-Capacitor __ Modulators 94

3.2 Finite Amplifier Gain in SC-__Ms 96

3.3 Capacitor Mismatch in SC-__Ms 99

3.4 Integrator Settling Error in SC-__Ms 102

3.4.1 Behavioral Model for the Integrator Settling 102

3.4.2 Linear Effect of Finite Amplifier Gain-Bandwidth Product 107

3.4.3 Nonlinear Effect of Finite Amplifier Slew Rate 109

3.4.4 Effect of Finite Switch On-Resistance 113

3.5 Circuit Noise in SC-__Ms 114

3.6 Clock Jitter in SC-__Ms 119

3.7 Sources of Distortion in SC-__Ms 121

3.7.1 Nonlinear Amplifier Gain 122

3.7.2 Nonlinear Switch On-Resistance 123

3.8 Case Study: High-Level Sizing of a __M 126

3.9 Summary 134

4 Circuits Errors and Compensation Techniques in Continuous-Time __ Modulators 139

4.1 Overview of Nonidealities in Continuous-Time __ Modulators 139

4.2 CT Integrators and Resonators 140

4.3 Finite Amplifier Gain in CT-__Ms 142

4.4 Time-Constant Error in CT-__Ms 144

4.5 Finite Integrator Dynamics in CT-__Ms 147

4.5.1 Effect of Finite Gain-Bandwidth on CT-__Ms 148

4.5.2 Effect of Finite Slew Rate on CT-__Ms 150

4.6 Sources of Distortion in CT-__Ms 151

4.6.1 Nonlinearities in the Front-End Integrator 151

4.6.2 Intersymbol Interference in the Feedback DAC 154

4.7 Circuit Noise in CT-__Ms 154

4.7.1 Noise analysis considering NRZ feedback DACs 155

4.7.2 Noise analysis considering SC feedback DACs 157

4.8 Clock Jitter in CT-__Ms 158

4.8.1 Jitter in Return-to-Zero DACs 159

4.8.2 Jitter in NonReturn-to-Zero DACs 161

4.8.3 Jitter in Switched-Capacitor DACs 162

4.8.4 Lingering Effect of Clock Jitter Error 163

4.8.5 Reducing the Effect of Clock Jitter with FIR and Sine-Shaped DACs 166

4.9 Excess Loop Delay in CT-__Ms 169

4.9.1 Intuitive analysis of ELD 170

4.9.2 Analysis of ELD based on impulse-invariant DT-CT transformation 172

4.9.3 Alternative ELD Compensation Techniques 174

4.10 Quantizer Metastability in CT-__Ms 176

4.11 Summary 181

5 Behavioral Modeling and High-Level Simulation 187

5.1 Systematic Design Methodology of __ Modulators 187

5.1.1 System Partitioning and Abstraction Levels 188

5.1.2 Sizing Process 189

5.2 Simulation Approaches for the High-Level Evaluation of __Ms 191

5.2.1 Alternatives to Transistor-Level Simulation 191

5.2.2 Event-Driven Behavioral Simulation Technique 193

5.2.3 Programming Languages and Behavioral Modeling Platforms 194

5.3 Implementing __M Behavioral Models 195

5.3.1 From Circuit Analysis to Computational Algorithms 196

5.3.2 Time-Domain versus Frequency-Domain Behavioral Models 198

5.3.3 Implementing Time-Domain Behavioral Models in MATLAB 201

5.3.4 Building Time-Domain Behavioral Models as SIMULINK C-MEX S-functions 207

5.4 Efficient Behavioral Modeling of __M Building Blocks using C-MEX S-functions 213

5.4.1 Modeling of SC Integrators using S-functions 213

5.4.2 Modeling of CT Integrators using S-functions 227

5.4.3 Behavioral Modeling of Quantizers using S-functions 231

5.5 SIMSIDES: A SIMULINK-Based Behavioral Simulator for __Ms 237

5.5.1 Model Libraries Included in SIMSIDES 238

5.5.2 Structure of SIMSIDES and User Interface 242

5.6 Using SIMSIDES for the High-Level Sizing and Verification of __Ms 245

5.6.1 SC Second-Order Single-Bit __M 247

5.6.2 CT Fifth-order Cascade 3-2 Multibit __M 255

5.7 Summary 262

6 Automated Design and Optimization of __Ms 267

6.1 Architecture Exploration and Selection: the Schreier’s Toolbox 268

6.1.1 Basic Functions of the Schreier’s Delta-Sigma Toolbox 268

6.1.2 Synthesis of a 4th-Order CRFF LP/BP SC-__M with Tunable Notch 271

6.1.3 Synthesis of a 4th-Order BP CT-__M with Tunable Notch 275

6.2 Optimization-based High-Level Synthesis of __ Modulators 279

6.2.1 Combining Behavioral Simulation and Optimization 280

6.2.2 Using Simulated Annealing as Optimization Engine 281

6.2.3 Combining SIMSIDES with MATLAB optimizers 288

6.3 Lifting Method and Hardware Acceleration to Optimize CT-__Ms 290

6.3.1 Hardware Emulation of CT-__Ms on an FPGA 293

6.3.2 GPU-accelerated Computing of CT-__Ms 294

6.4 Using Multi-Objective Evolutionary Algorithms to Optimize __Ms 297

6.4.1 Combining MOEA with SIMSIDES 298

6.4.2 Applying MOEA and SIMSIDES for the Synthesis of CT-__Ms 299

6.5 Summary 306

7 Electrical Design of __Ms: From Systems to Circuits 309

7.1 Macromodeling __Ms 310

7.1.1 SC Integrator Macromodel 310

7.1.2 CT Integrator Macromodel 313

7.1.3 Nonlinear OTA Transconductor 314

7.1.4 Embedded Flash ADC Macromodel 315

7.1.5 Feedback DAC Macromodel 316

7.2 Examples of __M Macromodels 318

7.2.1 SC Second-Order Example 318

7.2.2 Second-Order Active-RC __M 322

7.3 Including Noise in Transient Electrical Simulations of __Ms 323

7.3.1 Generating and Injecting Noise Data Sequences in HSPICE 324

7.3.2 Analyzing the Impact of Main Noise Sources in SC Integrators 329

7.3.3 Generating and Injecting Flicker Noise Sources in Electrical Simulations 329

7.3.4 Test Bench to Include Noise in the Simulation of __Ms 332

7.4 Processing __M Output Results of Electrical Simulations 336

7.5 Summary 339

8 Design Considerations of __M Subcircuits 341

8.1 Design Considerations of CMOS Switches 341

8.1.1 Trade-Off Between R and the CMOS Switch Drain/Source Parasitic Capacitances 342

8.1.3 Influence of Technology Downscaling on the Design of Switches 344

8.1.4 Evaluating Harmonic Distortion due to CMOS Switches 344

8.2 Design Considerations of Operational Amplifiers 350

8.2.1 Typical Amplifier Topologies 350

8.2.2 Common-Mode Feedback Networks 352

8.2.3 Characterization of the Amplifier in AC 353

8.2.4 Characterization of the Amplifier in DC 358

8.2.5 Characterization of the Amplifier Gain Nonlinearity 359

8.3 Design Considerations of Transconductors 359

8.3.1 Highly Linear Front-End Transconductor 362

8.3.2 Loop-Filter Transconductors 363

8.3.3 Widely Programmable Transconductors 367

8.4 Design Considerations of Comparators 368

8.4.1 Regenerative Latch-Based Comparators 369

8.4.2 Design Guidelines of Comparators 371

8.4.3 Characterization of Offset and Hysteresis Based on the Input-Ramp

8.1.2 Characterizing the Nonlinear Behavior of R on Method 373

8.4.4 Characterization of Offset and Hysteresis Based on the Bisectional Method 374

8.4.5 Characterizing the Comparison Time 375

8.5 Design Considerations of Current-Steering DACs 377

8.5.1 Fundamentals and Basic Concepts of CS DACs 378

8.5.2 Practical Realization of CS DACs 379

8.5.3 Current Cell Circuits, Error Limitations, and Design Criteria 381

8.5.4 CS 4-bit DAC Example 382

8.6 Summary 384

9 Practical Realization of __Ms: From Circuits to Chips 387

9.1 Auxiliary __M Building Blocks 387

9.1.1 Clock-Phase Generators 387

9.1.2 Generation of Common-Mode Voltage, Reference Voltage, and Bias Currents 390

9.1.3 Additional Digital Logic 393

9.2 Layout Design, Floorplanning, and Practical Issues 394

9.2.1 Layout Floorplanning 395

9.2.2 I/O Pad Ring 397

9.2.3 Importance of Layout Verification and Catastrophic Failures 397

9.3 Chip Package, Test PCB, and Experimental Set-Up 400

9.3.1 Bonding Diagram and Package 402

9.3.2 Test PCB 402

9.4 Experimental Test Set-Up 404

9.4.1 Planning the types and number of equipments needed 404

9.4.2 Connecting lab instruments 405

9.4.3 Measurement Set-Up Example 406

9.5 __M Design Examples and Case Studies 409

9.5.1 Programmable-Gain __Ms for High Dynamic-Range Sensor Interfaces 409

9.5.2 Reconfigurable SC-__Ms for Multi-Standard Direct Conversion Receivers 414

9.5.3 Using Widely-Programmable Gm-LC BP-__Ms for RF Digitizers 419

9.6 Summary 436

10 Frontiers, Trends and Challenges: Towards Next-Generations of __ Modulators 439

10.1 State-of-the-Art ADCs: Nyquist-Rate versus __ Converters 440

10.1.1 Conversion Energy 441

10.1.2 Figures of Merit 442

10.2 Comparison of Different Categories of __ ADCs 444

10.2.1 Aperture Plot of __Ms 445

10.2.2 Energy Plot of __Ms 446

10.3 Empirical and Statistical Analysis of State-of-the-Art __Ms 447

10.3.1 SC versus CT __Ms 447

10.3.2 Technology used in State-of-the-Art __Ms 449

10.3.3 Single-Loop versus Cascade __Ms 450

10.3.4 Single-Bit versus Multibit __Ms 452

10.3.5 Low-Pass versus Band-Pass __Ms 453

10.3.6 Emerging __M Techniques 455

10.4 GHz-Range __Ms for RF-to-digital Conversion 456

10.5 Enhanced Cascade __Ms 459

10.5.1 SMASH CT-__Ms 459

10.5.2 Two-stage 0-L MASH 460

10.5.3 Stage-Sharing Cascade __Ms 460

10.5.4 Multirate and Hybrid CT/DT __Ms 461

10.6 Power-Efficient __M Loop-Filter Techniques 465

10.6.1 Inverter-based __Ms 465

10.6.2 Hybrid Active/Passive & Amplifier-Less __Ms 466

10.6.3 Power-Efficient Amplifier Techniques 469

10.7 Hybrid __M/Nyquist-Rate ADCs 470

10.7.1 Multi-bit __M Quantizers based on Nyquist-rate ADCs 471

10.7.2 Incremental __ ADCs 473

10.8 Time-based __ ADCs 474

10.8.1 __Ms with VCO/PWM-based Quantization 475

10.8.2 Scaling-friendly mostly-digital __Ms 477

10.8.3 GRO-based __Ms 479

10.9 DAC Techniques for High-Performance CT-__Ms 480

10.10 Classification of State-of-the-Art References 482

10.11 Summary and Conclusions 482

A State-Space Analysis of Clock Jitter in CT-__Ms 523

A.1 State-Space Representation of NTF(z) 523

A.2 Expectation value of (_q 525

A.3 In-band noise power due to clock jitter 526

B SIMSIDES User Guide 529

B.1 Getting Started: Installing and Running SIMSIDES 529

B.2 Building and Editing __M Architectures in SIMSIDES 530

B.3 Analyzing __Ms in SIMSIDES 533

B.4 Optimization Interface 539

B.5 Tutorial Example: Using SIMSIDES to Model and Analyze __Ms 542

B.6 Getting Help 551

C SIMSIDES Block Libraries and Models 553

C.1 Overview of SIMSIDES Libraries 553

C.2 Ideal Libraries 553

C.2.1 Ideal Integrators 553

C.2.2 Ideal Resonators 555

C.2.3 Ideal Quantizers 556

C.2.4 Ideal D/A Converters 558

C.3 Real SC Building-Block Libraries 559

C.3.1 Real SC Integrators 560

C.3.2 Real SC Resonators 561

C.4 Real SI Building-Block Libraries 566

C.4.1 Real SI Integrators 566

C.4.2 Real SI Resonators 568

C.4.3 SI Errors and Model Parameters 568

C.5 Real CT Building-Block Libraries 572

C.5.1 Real CT Integrators 572

C.5.2 Real CT Resonators 578

C.6 Real Quantizers & Comparators 582

C.7 Real D/A Converters 582

C.8 Auxiliary Blocks 583