# Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

# Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

ISBN: 978-0-471-74141-1

Mar 2006

576 pages

$151.99

## Description

A new approach to the study of arithmetic circuitsIn Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems, the authors take a novel approach of presenting methods and examples for the synthesis of arithmetic circuits that better reflects the needs of today's computer system designers and engineers. Unlike other publications that limit discussion to arithmetic units for general-purpose computers, this text features a practical focus on embedded systems.

Following an introductory chapter, the publication is divided into two parts. The first part, Mathematical Aspects and Algorithms, includes mathematical background, number representation, addition and subtraction, multiplication, division, other arithmetic operations, and operations in finite fields. The second part, Synthesis of Arithmetic Circuits, includes hardware platforms, general principles of synthesis, adders and subtractors, multipliers, dividers, and other arithmetic primitives. In addition, the publication distinguishes itself with:

* A separate treatment of algorithms and circuits-a more useful presentation for both software and hardware implementations

* Complete executable and synthesizable VHDL models available on the book's companion Web site, allowing readers to generate synthesizable descriptions

* Proposed FPGA implementation examples, namely synthesizable low-level VHDL models for the Spartan II and Virtex families

* Two chapters dedicated to finite field operations

This publication is a must-have resource for students in computer science and embedded system designers, engineers, and researchers in the field of hardware and software computer system design and development.

An Instructor Support FTP site is available from the Wiley editorial department.

About the Authors.

**1. Introduction.**

1.1 Number Representation.

1.2 Algorithms.

1.3 Hardware Platforms.

1.4 Hardware–Software Partitioning.

1.5 Software Generation.

1.6 Synthesis.

1.7 A First Example.

1.7.1 Specification.

1.7.2 Number Representation.

1.7.3 Algorithms.

1.7.4 Hardware Platform.

1.7.5 Hardware–Software Partitioning.

1.7.6 Program Generation.

1.7.7 Synthesis.

1.7.8 Prototype.

1.8 Bibliography.

**2. Mathematical Background.**

2.1 Number Theory.

2.1.1 Basic Definitions.

2.1.2 Euclidean Algorithms.

2.1.3 Congruences.

2.2 Algebra.

2.2.1 Groups.

2.2.2 Rings.

2.2.3 Fields.

2.2.4 Polynomial Rings.

2.2.5 Congruences of Polynomial.

2.3 Function Approximation.

2.4 Bibliography.

**3. Number Representation.**

3.1 Natural Numbers.

3.1.1 Weighted Systems.

3.1.2 Residue Number System.

3.2 Integers.

3.2.1 Sign-Magnitude Representation.

3.2.2 Excess-E Representation.

3.2.3 B’s Complement Representation.

3.2.4 Booth’s Encoding.

3.3 Real Numbers.

3.4 Bibliography.

**4. Arithmetic Operations: Addition and Subtraction.**

4.1 Addition of Natural Numbers.

4.1.1 Basic Algorithm.

4.1.2 Faster Algorithms.

4.1.3 Long-Operand Addition.

4.1.4 Multioperand Addition.

4.1.5 Long-Multioperand Addition.

4.2 Subtraction of Natural Numbers.

4.3 Integers.

4.3.1 B’s Complement Addition.

4.3.2 B’s Complement Sign Change.

4.3.3 B’s Complement Subtraction.

4.3.4 B’s Complement Overflow Detection.

4.3.5 Excess-E Addition and Subtraction.

4.3.6 Sign–Magnitude Addition and Subtraction.

4.4 Bibliography.

**5. Arithmetic Operations: Multiplication.**

5.1 Natural Numbers Multiplication.

5.1.1 Introduction.

5.1.2 Shift and Add Algorithms.

5.1.2.1 Shift and Add 1.

5.1.2.2 Shift and Add 2.

5.1.2.3 Extended Shift and Add Algorithm: XY þ C þ D.

5.1.2.4 Cellular Shift and Add.

5.1.3 Long-Operand Algorithm.

5.2 Integers.

5.2.1 B’s Complement Multiplication.

5.2.1.1 Mod Bnþm B’s Complement Multiplication.

5.2.1.2 Signed Shift and Add.

5.2.1.3 Postcorrection B’s Complement Multiplication.

5.2.2 Postcorrection 2’s Complement Multiplication.

5.2.3 Booth Multiplication for Binary Numbers.

5.2.3.1 Booth-r Algorithms.

5.2.3.2 Per Gelosia Signed-Digit Algorithm.

5.2.4 Booth Multiplication for Base-B Numbers (Booth-r Algorithm in Base B).

5.3 Squaring.

5.3.1 Base-B Squaring.

5.3.1.1 Cellular Carry–Save Squaring Algorithm.

5.3.2 Base-2 Squaring.

5.4 Bibliography.

**6 Arithmetic Operations: Division.**

6.1 Natural Numbers.

6.2 Integers.

6.2.1 General Algorithm.

6.2.2 Restoring Division Algorithm.

6.2.3 Base-2 Nonrestoring Division Algorithm.

6.2.4 SRT Radix-2 Division.

6.2.5 SRT Radix-2 Division with Stored-Carry Encoding.

6.2.6 P–D Diagram.

6.2.7 SRT-4 Division.

6.2.8 Base-B Nonrestoring Division Algorithm.

6.3 Convergence (Functional Iteration) Algorithms.

6.3.1 Introduction.

6.3.2 Newton–Raphson Iteration Technique.

6.3.3 MacLaurin Expansion—Goldschmidt’s Algorithm.

6.4 Bibliography.

**7. Other Arithmetic Operations.**

7.1 Base Conversion.

7.2 Residue Number System Conversion.

7.2.1 Introduction.

7.2.2 Base-B to RNS Conversion.

7.2.3 RNS to Base-B Conversion.

7.3 Logarithmic, Exponential, and Trigonometric Functions.

7.3.1 Taylor–MacLaurin Series.

7.3.2 Polynomial Approximation.

7.3.3 Logarithm and Exponential Functions Approximation by Convergence Methods.

7.3.3.1 Logarithm Function Approximation by Multiplicative Normalization.

7.3.3.2 Exponential Function Approximation by Additive Normalization.

7.3.4 Trigonometric Functions—CORDIC Algorithms.

7.4 Square Rooting.

7.4.1 Digit Recurrence Algorithm—Base-B Integers.

7.4.2 Restoring Binary Shift-and-Subtract Square Rooting Algorithm.

7.4.3 Nonrestoring Binary Add-and-Subtract Square Rooting Algorithm.

7.4.4 Convergence Method—Newton–Raphson.

7.5 Bibliography.

**8. Finite Field Operations.**

8.1 Operations in Zm.

8.1.1 Addition.

8.1.2 Subtraction.

8.1.3 Multiplication.

8.1.3.1 Multiply and Reduce.

8.1.3.2 Modified Shift-and-Add Algorithm.

8.1.3.3 Montgomery Multiplication.

8.1.3.4 Specific Ring.

8.1.4 Exponentiation.

8.2 Operations in GF(p).

8.3 Operations in Zp[x]/f (x).

8.3.1 Addition and Subtraction.

8.3.2 Multiplication.

8.4 Operations in GF(pn).

8.5 Bibliography.

Appendix 8.1 Computation of fki.

**9 Hardware Platforms.**

9.1 Design Methods for Electronic Systems.

9.1.1 Basic Blocks of Integrated Systems.

9.1.2 Recurring Topics in Electronic Design.

9.1.2.1 Design Challenge: Optimizing Design Metrics.

9.1.2.2 Cost in Integrated Circuits.

9.1.2.3 Moore’s Law.

9.1.2.4 Time-to-Market.

9.1.2.5 Performance Metric.

9.1.2.6 The Power Dimension.

9.2 Instruction Set Processors.

9.2.1 Microprocessors.

9.2.2 Microcontrollers.

9.2.3 Embedded Processors Everywhere.

9.2.4 Digital Signal Processors.

9.2.5 Application-Specific Instruction Set Processors.

9.2.6 Programming Instruction Set Processors.

9.3 ASIC Designs.

9.3.1 Full-Custom ASIC.

9.3.2 Semicustom ASIC.

9.3.2.1 Gate-Array ASIC.

9.3.2.2 Standard-Cell-Based ASIC.

9.3.3 Design Flow in ASIC.

9.4 Programmable Logic.

9.4.1 Programmable Logic Devices (PLDs).

9.4.2 Field Programmable Gate Array (FPGA).

9.4.2.1 Why FPGA? A Short Historical Survey.

9.4.2.2 Basic FPGA Concepts.

9.4.3 XilinxTM Specifics.

9.4.3.1 Configurable Logic Blocks (CLBs).

9.4.3.2 Input/Output Blocks (IOBs).

9.4.3.3 RAM Blocks.

9.4.3.4 Programmable Routing.

9.4.3.5 Arithmetic Resources in Xilinx FPGAs.

9.4.4 FPGA Generic Design Flow.

9.5 Hardware Description Languages (HDLs).

9.5.1 Today’s and Tomorrow’s HDLs.

9.6 Further Readings.

9.7 Bibliography.

**10. Circuit Synthesis: General Principles.**

10.1 Resources.

10.2 Precedence Relation and Scheduling.

10.3 Pipeline.

10.4 Self-Timed Circuits.

10.5 Bibliography.

**11 Adders and Subtractors.**

11.1 Natural Numbers.

11.1.1 Basic Adder (Ripple-Carry Adder).

11.1.2 Carry-Chain Adder.

11.1.3 Carry-Skip Adder.

11.1.4 Optimization of Carry-Skip Adders.

11.1.5 Base-Bs Adder.

11.1.6 Carry-Select Adder.

11.1.7 Optimization of Carry-Select Adders.

11.1.8 Carry-Lookahead Adders (CLAs).

11.1.9 Prefix Adders.

11.1.10 FPGA Implementation of Adders.

11.1.10.1 Carry-Chain Adders.

11.1.10.2 Carry-Skip Adders.

11.1.10.3 Experimental Results.

11.1.11 Long-Operand Adders.

11.1.12 Multioperand Adders.

11.1.12.1 Sequential Multioperand Adders.

11.1.12.2 Combinational Multioperand Adders.

11.1.12.3 Carry-Save Adders.

11.1.12.4 Parallel Counters.

11.1.13 Subtractors and Adder-Subtractors.

11.1.14 Termination Detection.

11.1.15 FPGA Implementation of the Termination Detection.

11.2 Integers.

11.2.1 B’s Complement Adders and Subtractors.

11.2.2 Excess-E Adders and Subtractors.

11.2.3 Sign-Magnitude Adders and Subtractors.

11.3 Bibliography.

**12 Multipliers.**

12.1 Natural Numbers.

12.1.1 Basic Multiplier.

12.1.2 Sequential Multipliers.

12.1.3 Cellular Multiplier Arrays.

12.1.3.1 Ripple-Carry Multiplier.

12.1.3.2 Carry-Save Multiplier.

12.1.3.3 Figures of Merit.

12.1.4 Multipliers Based on Dissymmetric Br Bs Cells.

12.1.5 Multipliers Based on Multioperand Adders.

12.1.6 Per Gelosia Multiplication Arrays.

12.1.6.1 Introduction.

12.1.6.2 Adding Tree for Base-B Partial Products.

12.1.7 FPGA Implementation of Multipliers.

12.2 Integers.

12.2.1 B’s Complement Multipliers.

12.2.2 Booth Multipliers.

12.2.2.1 Booth-1 Multiplier.

12.2.2.2 Booth-2 Multiplier.

12.2.2.3 Signed-Digit Multiplier.

12.2.3 FPGA Implementation of the Booth-1 Multiplier.

12.3 Bibliography.

**13. Dividers.**

13.1 Natural Numbers.

13.2 Integers.

13.2.1 Base-2 Nonrestoring Divider.

13.2.2 Base-B Nonrestoring Divider.

13.2.3 SRT Dividers.

13.2.3.1 SRT-2 Divider.

13.2.3.2 SRT-2 Divider with Carry-Save Computation of the Remainder.

13.2.3.3 FPGA Implementation of the Carry-Save SRT-2 Divider.

13.2.4 SRT-4 Divider.

13.2.5 Convergence Dividers.

13.2.5.1 Newton–Raphson Divider.

13.2.5.2 Goldschmidt Divider.

13.2.5.3 Comparative Data Between Newton–Raphson (NR) and Goldschmidt (G) Implementations.

13.3 Bibliography.

**14 Other Arithmetic Operators.**

14.1 Base Conversion.

14.1.1 General Base Conversion.

14.1.2 BCD to Binary Converter.

14.1.2.1 Nonrestoring 2p Subtracting Implementation.

14.1.2.2 Shift-and-Add BCD to Binary Converter.

14.1.3 Binary to BCD Converter.

14.1.4 Base-B to RNS Converter.

14.1.5 CRT RNS to Base-B Converter.

14.1.6 RNS to Mixed-Radix System Converter.

14.2 Polynomial Computation Circuits.

14.3 Logarithm Operator.

14.4 Exponential Operator.

14.5 Sine and Cosine Operators.

14.6 Square Rooters.

14.6.1 Restoring Shift-and-Subtract Square Rooter (Naturals).

14.6.2 Nonrestoring Shift-and-Subtract Square Rooter (Naturals).

14.6.3 Newton–Raphson Square Rooter (Naturals).

14.7 Bibliography.

**15. Circuits for Finite Field Operations.**

15.1 Operations in Zm.

15.1.1 Adders and Subtractors.

15.1.2 Multiplication.

15.1.2.1 Multiply and Reduce.

15.1.2.2 Shift and Add.

15.1.2.3 Montgomery Multiplication.

15.1.2.4 Modulo (Bk*2*c) Reduction.

15.1.2.5 Exponentiation.

15.2 Inversion in GF(p).

15.3 Operations in Zp[x]/f (x).

15.4 Inversion in GF(pn).

15.5 Bibliography.

**16. Floating-Point Unit.**

16.1 Floating-Point System Definition.

16.2 Arithmetic Operations.

16.2.1 Addition of Positive Numbers.

16.2.2 Difference of Positive Numbers.

16.2.3 Addition and Subtraction.

16.2.4 Multiplication.

16.2.5 Division.

16.2.6 Square Root.

16.3 Rounding Schemes.

16.4 Guard Digits.

16.5 Adder-Subtractor.

16.5.1 Alignment.

16.5.2 Additions.

16.5.3 Normalization.

16.5.4 Rounding.

16.6 Multiplier.

16.7 Divider.

16.8 Square Root.

16.9 Comments.

16.10 Bibliography.

**Index.**

*IEEE Circuits & Devices Magazine*, November/December 2006)

""This book is warmly recommended to anyone having to design or understand how computer arithmetic operates at almost every conceivable level of detail."" (*Computing Reviews.com*, June 8, 2006)