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This item: Tradeoffs and Optimization in Analog CMOS Design
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List of Symbols and Abbreviations.
1.1 Importance of Tradeoffs and Optimization in Analog CMOS Design.
1.2 Industry Designers and University Students as Readers.
1.3 Organization and Overview of Book.
1.4 Full or Selective Reading of Book.
1.5 Example Technologies and Technology Extensions.
1.6 Limitations of the Methods.
PART I MOS Device Performance, Tradeoffs and Optimization for Analog CMOS Design.
2 MOS Design from Weak through Strong Inversion.
2.2 MOS Design Complexity Compared to Bipolar Design.
2.3 Bipolar Transistor Collector Current and Transconductance.
2.4 MOS Drain Current and Transconductance.
2.5 MOS Drain–Source Conductance.
2.6 Analog CMOS Electronic Design Automation Tools and Design Methods.
3 MOS Performance versus Drain Current, Inversion Coefficient, and Channel Length.
3.2 Advantages of Selecting Drain Current, Inversion Coefficient, and Channel Length in Analog CMOS Design.
3.3 Process Parameters for Example Processes.
3.4 Substrate Factor and Inversion Coefficient.
3.5 Temperature Effects.
3.6 Sizing Relationships.
3.7 Drain Current and Bias Voltages.
3.8 Small-Signal Parameters and Intrinsic Voltage Gain.
3.9 Capacitances and Bandwidth.
3.12 Leakage Current.
4 Tradeoffs in MOS Performance, and Design of Differential Pairs and Current Mirrors.
4.2 Performance Trends.
4.3 Performance Tradeoffs.
4.4 Design of Differential Pairs and Current Mirrors Using the Analog CMOS Design, Tradeoffs and Optimization Spreadsheet.
PART II Circuit Design Examples Illustrating Optimization for Analog CMOS Design.
5 Design of CMOS Operational Transconductance Amplifiers Optimized for DC, Balanced, and AC Performance.
5.2 Circuit Description.
5.3 Circuit Analysis and Performance Optimization.
5.4 Design Optimization and Resulting Performance for the Simple OTAs.
5.5 Design Optimization and Resulting Performance for the Cascoded OTAs.
5.6 Prediction Accuracy for Design Guidance and Optimization.
6 Design of Micropower CMOS Preamplifiers Optimized for Low Thermal and Flicker Noise.
6.2 Using the Lateral Bipolar Transistor for Low-Flicker-Noise Applications.
6.3 Measures of Preamplifier Noise Performance.
6.4 Reported Micropower, Low-Noise CMOS Preamplifiers.
6.5 MOS Noise versus the Bias Compliance Voltage.
6.6 Extraction of MOS Flicker-Noise Parameters.
6.7 Differential Input Preamplifier.
6.8 Single-Ended Input Preamplifier.
6.9 Prediction Accuracy for Design Guidance and Optimization.
6.10 Summary of Low-Noise Design Methods and Resulting Challenges in Low-Voltage Processes.
7 Extending Optimization Methods to Smaller-Geometry CMOS Processes and Future Technologies.
7.2 Using the Inversion Coefficient for CMOS Process Independence and for Extension to Smaller-Geometry Processes.
7.3 Enhancing Optimization Methods by Including Gate Leakage Current Effects.
7.4 Using an Inversion Coefficient Measure for Non-CMOS Technologies.
Appendix: The Analog CMOS Design, Tradeoffs and Optimization Spreadsheet.