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Verilog Coding for Logic Synthesis

Verilog Coding for Logic Synthesis

Weng Fook Lee

ISBN: 978-0-471-45756-5

Jan 2005

309 pages


Provides a practical approach to Verilog design and problem solving.
* Bulk of the book deals with practical design problems that design engineers solve on a daily basis.
* Includes over 90 design examples.
* There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.
* Book is suitable for use as a textbook in EE departments that have VLSI courses

Related Resources


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Table of Figures.

Table of Examples.

List of Tables.





Asic Design Flow.

Verilog Coding.

Coding Style: Best-Known Method for Synthesis.

Design Example of Programmable Timer.

Design Example of Programmable Logic Block for Peripheral Interface.